Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.85	89.96		88.59			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T55,T225,T226	Yes	T55,T225,T226	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T32,T204,T113	Yes	T32,T204,T113	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T32,T204,T113	Yes	T32,T204,T113	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T44,T227,T169	Yes	T44,T227,T169	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T44,T227,T169	Yes	T44,T227,T169	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T32,T76,T77	Yes	T32,T76,T77	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T32,T46,T44	Yes	T32,T46,T44	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T32,T46,T44	Yes	T32,T46,T44	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T32,T46,T44	Yes	T32,T46,T44	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T32,T46,T44	Yes	T32,T46,T44	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T46,T44,T98	Yes	T46,T44,T98	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T32,T46,T44	Yes	T32,T46,T44	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T32,*T46,*T44	Yes	T32,T46,T44	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T32,T46,T44	Yes	T32,T46,T44	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T55,T56,T59	Yes	T54,T55,T56	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T32,T64,T65	Yes	T32,T64,T65	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T32,T64,T65	Yes	T32,T64,T65	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T32,T64,T65	Yes	T32,T64,T65	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T32,T64,T65	Yes	T32,T64,T65	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T32,T64,T65	Yes	T32,T64,T65	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T32,*T64,*T65	Yes	T32,T64,T65	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T32,T64,T65	Yes	T32,T64,T65	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T32,T4	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T32,T64,T65	Yes	T32,T64,T65	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T64,T65	Yes	T32,T64,T65	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T32,T4	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T32,*T64,*T65	Yes	T32,T64,T65	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T32,T4	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T32,T64,T65	Yes	T32,T64,T65	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T5,T6,T88	Yes	T5,T6,T88	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T63,T95,T96	Yes	T63,T95,T96	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T63,T376	Yes	T4,T63,T376	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T63,T376	Yes	T4,T63,T376	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T63,T95,T96	Yes	T63,T95,T96	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T4,T63,T376	Yes	T4,T63,T376	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T4,T63,T376	Yes	T4,T63,T376	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T4,T63,T376	Yes	T4,T63,T376	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T55,T59,T103	Yes	T55,T59,T103	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T4,T376,T377	Yes	T4,T376,T377	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T55,T59	Yes	T63,T95,T96	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T4,T376,T377	Yes	T4,T63,T376	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T55,T56,T59	Yes	T54,T55,T59	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T55,*T59,*T103	Yes	T54,T55,T56	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T4,*T378,*T379	Yes	T4,T376,T377	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T4,T63,T376	Yes	T4,T63,T376	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T77,T87,T324	Yes	T77,T87,T324	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T63,T358,T10	Yes	T63,T358,T10	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T63,T358,T10	Yes	T63,T358,T10	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T63,T358,T10	Yes	T63,T358,T10	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T63,T358,T10	Yes	T63,T358,T10	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T63,T358,T10	Yes	T63,T358,T10	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T63,T358,T10	Yes	T63,T358,T10	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T55,T59,T103	Yes	T55,T59,T103	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T11,T187,T188	Yes	T11,T187,T188	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T63,T358,T10	Yes	T63,T358,T10	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T63,T358,T10	Yes	T63,T358,T10	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T55,T59,T103	Yes	T54,T55,T59	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T358,T10,T11	Yes	T358,T10,T11	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T358,T10,T11	Yes	T63,T358,T10	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T358,T10,T11	Yes	T358,T10,T11	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T54,T55,T59	Yes	T54,T55,T56	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T55,*T59,*T103	Yes	T54,T55,T56	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T55,T59,T103	Yes	T55,T59,T103	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T358,*T10,*T11	Yes	T358,T10,T11	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T63,T358,T10	Yes	T63,T358,T10	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T63,T33,T358	Yes	T63,T33,T358	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T63,T33,T358	Yes	T63,T33,T358	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T63,T33,T358	Yes	T63,T33,T358	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T63,T33,T358	Yes	T63,T33,T358	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T63,T33,T358	Yes	T63,T33,T358	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T63,T33,T358	Yes	T63,T33,T358	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T63,T33,T358	Yes	T63,T33,T358	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T63,T33,T358	Yes	T63,T33,T358	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T33,T358,T370	Yes	T33,T358,T370	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T33,T358,T371	Yes	T63,T33,T358	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T33,T358,T370	Yes	T33,T358,T370	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T55,*T56,*T59	Yes	T54,T55,T56	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T33,*T358,*T371	Yes	T33,T358,T371	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T63,T33,T358	Yes	T63,T33,T358	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T16,T63,T17	Yes	T16,T63,T17	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T16,T63,T17	Yes	T16,T63,T17	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T16,T63,T17	Yes	T16,T63,T17	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T16,T63,T17	Yes	T16,T63,T17	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T16,T63,T17	Yes	T16,T63,T17	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T16,T63,T17	Yes	T16,T63,T17	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T57,*T169,*T54	Yes	T57,T169,T54	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T55,T56,T59	Yes	T55,T56,T59	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T16,T63,T17	Yes	T16,T63,T17	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T16,T63,T17	Yes	T16,T63,T17	INPUT
tl_usbdev_i.d_error	Yes	Yes	T55,T59,T103	Yes	T55,T59,T103	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T17,T22,T369	Yes	T17,T22,T369	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T22,T369	Yes	T17,T22,T369	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T16,T63,T17	Yes	T16,T17,T18	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T55,T56,T59	Yes	T55,T56,T59	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T57,*T169,*T55	Yes	T57,T169,T54	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T55,T56,T59	Yes	T55,T56,T59	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T16,*T63,*T17	Yes	T16,T17,T18	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T16,T63,T17	Yes	T16,T63,T17	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T58,*T54,*T55	Yes	T58,T54,T55	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T32,T4	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T32,T4	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T58,*T55,*T56	Yes	T58,T54,T55	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T58,T54,T55	Yes	T58,T54,T55	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T58,T54,T55	Yes	T58,T54,T55	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T58,T54,T55	Yes	T58,T54,T55	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T58,T54,T55	Yes	T58,T54,T55	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T58,T54,T55	Yes	T58,T54,T55	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T58,*T54,T55	Yes	T58,T54,T55	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T58,T54,T55	Yes	T58,T54,T55	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T58,T54,T55	Yes	T58,T54,T55	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T54,T55,T59	Yes	T54,T55,T56	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T56	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T58,T54,T55	Yes	T58,T54,T55	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T58,T54,T55	Yes	T58,T54,T55	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T59	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T58,T54,T55	Yes	T58,T54,T55	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T58,*T54,*T55	Yes	T58,T54,T55	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T58,T54,T55	Yes	T58,T54,T55	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T32,T4	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T58,*T54,*T55	Yes	T58,T54,T55	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T375,T319,T660	Yes	T375,T319,T660	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	INPUT
tl_hmac_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	INPUT
tl_hmac_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T58,*T55,*T56	Yes	T58,T54,T55	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T41	Yes	T5,T6,T41	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	INPUT
tl_kmac_o.d_ready	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T63,T85,T173	Yes	T63,T85,T173	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T63,T85,T174	Yes	T63,T85,T174	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T63,T85,T174	Yes	T63,T85,T174	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T63,T173,T175	Yes	T63,T173,T175	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T63,T85,T174	Yes	T63,T85,T174	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T58,*T54,*T55	Yes	T58,T54,T55	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T175,T176,T177	Yes	T175,T176,T177	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T63,T85,T174	Yes	T63,T85,T174	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T63,T85,T174	Yes	T63,T85,T174	INPUT
tl_kmac_i.d_error	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T85,T174,T173	Yes	T85,T174,T173	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T85,T174,T173	Yes	T85,T174,T173	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T63,T85,T173	Yes	T173,T175,T60	INPUT
tl_kmac_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T59	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T58,*T55,*T56	Yes	T58,T54,T55	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T56	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T63,*T85,*T173	Yes	T175,T60,T176	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T63,T85,T174	Yes	T63,T85,T174	INPUT
tl_aes_o.d_ready	Yes	Yes	T1,T32,T91	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T91,T63,T657	Yes	T91,T63,T657	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T91,T63,T657	Yes	T91,T63,T657	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T91,T76,T63	Yes	T91,T76,T63	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T91,T63,T657	Yes	T91,T63,T657	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T91,T76,T63	Yes	T91,T76,T63	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T58,*T54,*T55	Yes	T58,T54,T55	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T91,T76,T63	Yes	T91,T76,T63	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T91,T76,T63	Yes	T91,T76,T63	INPUT
tl_aes_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T91,T76,T657	Yes	T91,T76,T657	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T91,T657,T658	Yes	T91,T63,T657	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T91,T76,T657	Yes	T91,T76,T63	INPUT
tl_aes_i.d_sink	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T58,*T55,*T59	Yes	T58,T54,T55	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T59	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T91,*T76,*T657	Yes	T91,T76,T657	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T91,T76,T63	Yes	T91,T76,T63	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T58,*T54,*T55	Yes	T58,T54,T55	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T55,T59,T103	Yes	T55,T59,T103	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T55,T59,T103	Yes	T55,T59,T103	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T93,T91,T85	Yes	T93,T91,T85	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T32,T93	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T55,T59,T103	Yes	T55,T59,T103	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T58,*T55,*T59	Yes	T58,T54,T55	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T93,*T91,*T85	Yes	T93,T91,T41	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T93,T91,T346	Yes	T93,T91,T346	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T58,*T55,*T56	Yes	T58,T55,T56	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T55,T56,T59	Yes	T55,T56,T59	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T54,T55,T59	Yes	T55,T56,T59	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T93,T91,T346	Yes	T93,T91,T346	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T32,T93	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T55,T56,T59	Yes	T54,T55,T56	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T58,*T55,*T59	Yes	T58,T55,T56	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T55,T56,T59	Yes	T55,T56,T59	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T93,*T91,*T346	Yes	T93,T91,T346	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T93,T91,T63	Yes	T93,T91,T63	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T93,T91,T63	Yes	T93,T91,T63	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T58,*T54,*T55	Yes	T58,T54,T55	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T93,T91,T85	Yes	T93,T91,T85	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T32,T93	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T1,T32,T93	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T58,*T55,*T59	Yes	T58,T54,T55	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T55,T59,T103	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T93,*T91,*T85	Yes	T93,T91,T85	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T32,T93	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T93,T91,T63	Yes	T93,T91,T63	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T93,T91,T63	Yes	T93,T91,T63	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T93,T91,T63	Yes	T93,T91,T63	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T93,T91,T63	Yes	T93,T91,T63	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T93,T91,T63	Yes	T93,T91,T63	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T58,*T54,*T55	Yes	T58,T54,T55	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T93,T91,T63	Yes	T93,T91,T63	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T93,T91,T63	Yes	T93,T91,T63	INPUT
tl_edn1_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T93,T91,T85	Yes	T93,T91,T85	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T93,T91,T85	Yes	T93,T91,T63	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T93,T91,T85	Yes	T93,T91,T63	INPUT
tl_edn1_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T58,*T55,*T56	Yes	T58,T54,T55	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T93,*T91,*T85	Yes	T93,T91,T85	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T93,T91,T63	Yes	T93,T91,T63	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T93	Yes	T1,T2,T93	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T93	Yes	T1,T2,T93	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T93	Yes	T1,T2,T93	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T1,T2,T93	Yes	T1,T2,T93	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T1,T2,T93	Yes	T1,T2,T93	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T1,T2,T93	Yes	T1,T2,T93	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T1,T2,T93	Yes	T1,T2,T93	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T2,T93,T76	Yes	T2,T93,T76	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T93	Yes	T1,T2,T93	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T1,T2,T93	Yes	T1,T2,T93	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T54,*T55,*T59	Yes	T54,T55,T56	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T93	Yes	T1,T2,T93	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T1,T2,T93	Yes	T1,T2,T93	INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T32,T93	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T93,T5,T6	Yes	T93,T5,T6	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T93,T5,T6	Yes	T93,T5,T6	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T93,T5,T6	Yes	T93,T5,T6	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T93,T5,T6	Yes	T93,T5,T6	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T93,T5,T6	Yes	T93,T5,T6	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T44,*T227,*T412	Yes	T44,T227,T412	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T93,T5,T6	Yes	T93,T5,T6	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T93,T5,T6	Yes	T93,T5,T6	INPUT
tl_otbn_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T59	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T93,T5,T6	Yes	T93,T5,T6	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T93,T5,T6	Yes	T93,T5,T6	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T93,T5,T6	Yes	T93,T5,T6	INPUT
tl_otbn_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T44,*T227,*T412	Yes	T44,T227,T412	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T93,*T5,*T6	Yes	T93,T5,T6	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T93,T5,T6	Yes	T93,T5,T6	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T45,T41,T205	Yes	T45,T41,T205	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T45,T41,T205	Yes	T45,T41,T205	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T45,T41,T205	Yes	T45,T41,T205	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T41,T205,T63	Yes	T41,T205,T63	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T45,T41,T205	Yes	T45,T41,T205	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T58,*T54,*T55	Yes	T58,T54,T55	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T45,T41,T205	Yes	T45,T41,T205	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T45,T41,T205	Yes	T45,T41,T205	INPUT
tl_keymgr_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T205,T85,T42	Yes	T205,T85,T42	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T41,T205	Yes	T45,T41,T205	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T45,T41,T205	Yes	T45,T41,T205	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T58,*T55,*T59	Yes	T58,T54,T55	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T41,*T205,*T85	Yes	T45,T41,T205	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T45,T41,T205	Yes	T45,T41,T205	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T55,T59,T103	Yes	T55,T56,T59	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T135,T276,T277	Yes	T135,T276,T277	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T132	Yes	T5,T6,T41	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T5,T6,T132	Yes	T5,T6,T41	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T54,T55,T59	Yes	T54,T55,T56	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T55,*T59,*T103	Yes	T54,T55,T56	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T132,*T133,*T135	Yes	T132,T133,T135	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T32,T4	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range