Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.85	89.96		88.59			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T77,T87,T324	Yes	T77,T87,T324	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T5,T200,T6	Yes	T5,T200,T6	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T5,T200,T6	Yes	T5,T200,T6	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T5,T200,T6	Yes	T5,T200,T6	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T5,T200,T6	Yes	T5,T200,T6	INPUT
tl_uart0_i.d_error	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T5,T200,T6	Yes	T5,T200,T6	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T200,T6	Yes	T5,T200,T6	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T5,T200,T6	Yes	T5,T200,T6	INPUT
tl_uart0_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T57,*T169,*T55	Yes	T57,T169,T54	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T55,T59,T103	Yes	T54,T55,T59	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T5,*T200,*T6	Yes	T5,T200,T6	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T5,T200,T6	Yes	T5,T200,T6	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T194,T116,T196	Yes	T194,T116,T196	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T194,T116,T196	Yes	T194,T116,T196	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T194,T63,T116	Yes	T194,T63,T116	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T194,T63,T116	Yes	T194,T63,T116	INPUT
tl_uart1_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T194,T116,T196	Yes	T194,T116,T196	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T194,T116,T196	Yes	T194,T63,T116	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T194,T116,T196	Yes	T194,T63,T116	INPUT
tl_uart1_i.d_sink	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T57,*T169,*T54	Yes	T57,T169,T54	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T194,*T116,*T196	Yes	T194,T116,T196	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T194,T63,T116	Yes	T194,T63,T116	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T170,T291,T303	Yes	T170,T291,T303	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T170,T291,T303	Yes	T170,T291,T303	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T63,T170,T291	Yes	T63,T170,T291	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T63,T170,T291	Yes	T63,T170,T291	INPUT
tl_uart2_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T170,T291,T303	Yes	T170,T291,T303	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T170,T291,T303	Yes	T63,T170,T291	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T170,T291,T303	Yes	T63,T170,T291	INPUT
tl_uart2_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T57,*T169,*T54	Yes	T57,T169,T54	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T170,*T291,*T303	Yes	T170,T291,T303	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T63,T170,T291	Yes	T63,T170,T291	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T14,T15,T292	Yes	T14,T15,T292	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T14,T15,T292	Yes	T14,T15,T292	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T63,T14,T15	Yes	T63,T14,T15	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T63,T14,T15	Yes	T63,T14,T15	INPUT
tl_uart3_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T59	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T14,T15,T292	Yes	T14,T15,T292	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T14,T15,T292	Yes	T63,T14,T15	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T14,T15,T292	Yes	T63,T14,T15	INPUT
tl_uart3_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T59	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T57,*T169,*T54	Yes	T57,T169,T54	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T14,*T15,*T292	Yes	T14,T15,T292	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T63,T14,T15	Yes	T63,T14,T15	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T290,T358,T293	Yes	T290,T358,T293	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T290,T358,T293	Yes	T290,T358,T293	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T63,T290,T358	Yes	T63,T290,T358	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T63,T290,T358	Yes	T63,T290,T358	INPUT
tl_i2c0_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T290,T293,T192	Yes	T290,T293,T192	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T290,T358,T293	Yes	T63,T290,T358	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T290,T358,T293	Yes	T63,T290,T358	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T58,*T54,*T55	Yes	T58,T54,T55	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T290,*T358,*T293	Yes	T290,T358,T293	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T63,T290,T358	Yes	T63,T290,T358	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T197,T290,T358	Yes	T197,T290,T358	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T197,T290,T358	Yes	T197,T290,T358	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T63,T197,T290	Yes	T63,T197,T290	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T63,T197,T290	Yes	T63,T197,T290	INPUT
tl_i2c1_i.d_error	Yes	Yes	T54,T55,T59	Yes	T55,T56,T59	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T197,T290,T293	Yes	T197,T290,T293	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T197,T290,T358	Yes	T63,T197,T290	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T197,T290,T358	Yes	T63,T197,T290	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T58,*T55,*T59	Yes	T58,T54,T55	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T55,T56,T59	Yes	T54,T55,T59	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T197,*T290,*T358	Yes	T197,T290,T358	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T63,T197,T290	Yes	T63,T197,T290	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T290,T358,T293	Yes	T290,T358,T293	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T290,T358,T293	Yes	T290,T358,T293	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T63,T290,T358	Yes	T63,T290,T358	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T63,T290,T358	Yes	T63,T290,T358	INPUT
tl_i2c2_i.d_error	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T290,T293,T199	Yes	T290,T293,T199	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T290,T358,T293	Yes	T63,T290,T358	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T290,T358,T293	Yes	T63,T290,T358	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T58,*T55,*T59	Yes	T58,T54,T55	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T290,*T358,*T293	Yes	T290,T358,T293	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T63,T290,T358	Yes	T63,T290,T358	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T310,T311,T128	Yes	T310,T311,T128	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T310,T311,T128	Yes	T310,T311,T128	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T63,T310,T311	Yes	T63,T310,T311	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T63,T310,T311	Yes	T63,T310,T311	INPUT
tl_pattgen_i.d_error	Yes	Yes	T55,T56,T59	Yes	T54,T55,T56	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T310,T311,T128	Yes	T310,T311,T128	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T310,T311,T128	Yes	T63,T310,T311	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T310,T311,T128	Yes	T63,T310,T311	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T55,T59,*T103	Yes	T54,T55,T56	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T56	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T310,*T311,*T128	Yes	T310,T311,T128	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T63,T310,T311	Yes	T63,T310,T311	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T198,T659,T230	Yes	T198,T659,T230	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T198,T659,T230	Yes	T198,T659,T230	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T63,T198,T659	Yes	T63,T198,T659	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T63,T198,T659	Yes	T63,T198,T659	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T59	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T198,T659,T230	Yes	T198,T659,T230	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T198,T659,T230	Yes	T63,T198,T659	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T198,T659,T230	Yes	T63,T198,T659	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T55,*T59,*T103	Yes	T54,T55,T56	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T198,*T659,*T230	Yes	T198,T659,T230	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T63,T198,T659	Yes	T63,T198,T659	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T13,T290,T293	Yes	T13,T290,T293	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T13,T290,T293	Yes	T13,T63,T25	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T13,T290,T293	Yes	T13,T63,T25	INPUT
tl_gpio_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T58,*T55,*T59	Yes	T58,T54,T55	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T1,*T32,*T4	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T2,T116,T165	Yes	T2,T116,T165	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T2,T116,T165	Yes	T2,T116,T165	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T2,T63,T116	Yes	T2,T63,T116	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T2,T63,T116	Yes	T2,T63,T116	INPUT
tl_spi_device_i.d_error	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T2,T116,T165	Yes	T2,T116,T165	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T116,T165	Yes	T2,T116,T165	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T2,T63,T116	Yes	T2,T116,T165	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T54,*T55,*T59	Yes	T54,T55,T59	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T59	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T2,*T63,*T116	Yes	T2,T116,T165	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T2,T63,T116	Yes	T2,T63,T116	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T3,T231,T232	Yes	T3,T231,T232	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T3,T231,T232	Yes	T3,T231,T232	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T3,T63,T231	Yes	T3,T63,T231	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T3,T63,T231	Yes	T3,T63,T231	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T3,T231,T232	Yes	T3,T231,T232	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T231,T232	Yes	T3,T63,T231	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T3,T231,T232	Yes	T3,T63,T231	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T55,*T59,*T103	Yes	T54,T55,T56	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T3,*T231,*T232	Yes	T3,T231,T232	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T3,T63,T231	Yes	T3,T63,T231	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T97,*T16	Yes	T1,T97,T16	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T55,*T59,*T103	Yes	T54,T55,T56	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T55,T56,T59	Yes	T54,T55,T56	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T93,T194,T200	Yes	T93,T194,T200	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T93,T194,T200	Yes	T93,T194,T200	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T194,T200,T14	Yes	T194,T200,T14	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T32,T93	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T58,*T55,*T56	Yes	T58,T54,T55	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T93,*T194,*T200	Yes	T93,T194,T200	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T59	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T55,*T59,*T103	Yes	T54,T55,T56	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T54,T55,T59	Yes	T55,T59,T103	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T45,*T63,*T85	Yes	T45,T85,T127	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T32,T4	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T55,T59,T103	Yes	T54,T55,T56	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T59	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T32,T4	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T55,T59,T103	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T55,T59,T103	Yes	T54,T55,T56	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T55,T59,T103	Yes	T55,T59,T103	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T32,T4	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T32,T4,T5	Yes	T32,T4,T5	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T32,T4,T5	Yes	T32,T4,T5	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T32,T4,T5	Yes	T32,T4,T5	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T32,T4,T5	Yes	T32,T4,T5	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T32,T5,T6	Yes	T32,T5,T6	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T60,T61,T62	Yes	T63,T60,T61	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T32,T4,T5	Yes	T32,T4,T5	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T32,*T64,*T65	Yes	T32,T64,T65	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T32,*T4,*T5	Yes	T32,T4,T5	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T32,T4,T5	Yes	T32,T4,T5	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T55,T59,T103	Yes	T55,T59,T103	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T149,T150,T162	Yes	T149,T150,T162	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T149,T150,T162	Yes	T149,T63,T150	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T59	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T55,*T59,*T103	Yes	T54,T55,T56	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T56	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T32,*T4	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T97,T70,T76	Yes	T97,T70,T76	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T97,T70,T76	Yes	T97,T70,T76	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T97,T70,T76	Yes	T97,T70,T76	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T97,T70,T76	Yes	T97,T70,T76	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T55,T56,T59	Yes	T54,T55,T56	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T97,T70,T76	Yes	T97,T70,T76	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T97,T70,T76	Yes	T97,T70,T76	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T97,T76,T77	Yes	T97,T70,T76	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T58,*T55,*T59	Yes	T58,T54,T55	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T55,T59,T103	Yes	T55,T59,T103	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T97,*T70,*T76	Yes	T97,T70,T76	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T97,T70,T76	Yes	T97,T70,T76	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T131,T132,T133	Yes	T131,T132,T133	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T131	Yes	T5,T6,T41	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T5,T6,T131	Yes	T5,T6,T41	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T54,*T55,*T59	Yes	T54,T55,T59	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T59	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T131,*T132,*T133	Yes	T131,T132,T133	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T5,T6,T41	Yes	T5,T6,T41	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T32,T97	Yes	T1,T32,T97	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T32,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T32,T97	Yes	T1,T32,T97	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T32,T97	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T1,T32,T97	Yes	T1,T32,T97	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T44,*T227,*T412	Yes	T44,T227,T412	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T58,*T55,*T56	Yes	T58,T54,T55	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T1,*T97,*T16	Yes	T1,T97,T16	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T1,T97,T16	Yes	T1,T97,T16	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T16,T45,T233	Yes	T16,T45,T233	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T16,T45,T233	Yes	T16,T45,T233	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T16,T45,T63	Yes	T16,T45,T63	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T16,T45,T63	Yes	T16,T45,T63	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T16,T233,T234	Yes	T16,T233,T234	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T45,T233	Yes	T16,T45,T63	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T45,T233,T234	Yes	T16,T45,T63	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T57,*T169,*T55	Yes	T57,T169,T54	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T54,T55,T59	Yes	T54,T55,T56	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T16,*T233,*T234	Yes	T16,T45,T233	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T16,T45,T63	Yes	T16,T45,T63	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T16,T45,T138	Yes	T16,T45,T138	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T16,T45,T138	Yes	T16,T45,T138	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T16,T45,T63	Yes	T16,T45,T63	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T16,T45,T63	Yes	T16,T45,T63	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T16,T138,T18	Yes	T16,T45,T138	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T45,T138	Yes	T16,T45,T63	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T16,T45,T138	Yes	T16,T45,T63	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T59	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T58,*T55,*T59	Yes	T58,T54,T55	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T59	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T16,*T138,*T18	Yes	T16,T45,T138	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T16,T45,T63	Yes	T16,T45,T63	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T59	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T54,T55,T59	Yes	T54,T55,T56	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T54,*T55,*T59	Yes	T54,T55,T56	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T55,T56,T59	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T59	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range