Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.32 94.12 89.29 100.00 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 91.67 100.00 66.67 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 84.62 100.00 100.00 u_edn_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 91.67 100.00 66.67 100.00 100.00

Line Coverage for Module : prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Module : prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 747589168 3964 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 747589168 3964 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 747589168 3964 0 0
T1 301011 4 0 0
T2 145559 1 0 0
T3 74838 1 0 0
T4 247113 1 0 0
T16 608791 12 0 0
T32 221084 2 0 0
T45 121858 2 0 0
T69 216471 0 0 0
T75 268842 0 0 0
T81 224345 0 0 0
T91 407722 1 0 0
T93 392002 1 0 0
T97 137592 2 0 0
T134 79911 5 0 0
T136 0 8 0 0
T137 0 8 0 0
T175 87330 0 0 0
T184 611380 0 0 0
T269 0 5 0 0
T270 0 8 0 0
T271 0 8 0 0
T272 247398 0 0 0
T273 141536 0 0 0
T274 103328 0 0 0
T275 746391 0 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 747589168 3964 0 0
T1 301011 4 0 0
T2 145559 1 0 0
T3 74838 1 0 0
T4 247113 1 0 0
T16 608791 12 0 0
T32 221084 2 0 0
T45 121858 2 0 0
T69 216471 0 0 0
T75 268842 0 0 0
T81 224345 0 0 0
T91 407722 1 0 0
T93 392002 1 0 0
T97 137592 2 0 0
T134 79911 5 0 0
T136 0 8 0 0
T137 0 8 0 0
T175 87330 0 0 0
T184 611380 0 0 0
T269 0 5 0 0
T270 0 8 0 0
T271 0 8 0 0
T272 247398 0 0 0
T273 141536 0 0 0
T274 103328 0 0 0
T275 746391 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 373794584 42 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 373794584 42 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 373794584 42 0 0
T69 216471 0 0 0
T75 268842 0 0 0
T81 224345 0 0 0
T134 79911 5 0 0
T136 0 8 0 0
T137 0 8 0 0
T175 87330 0 0 0
T184 611380 0 0 0
T269 0 5 0 0
T270 0 8 0 0
T271 0 8 0 0
T272 247398 0 0 0
T273 141536 0 0 0
T274 103328 0 0 0
T275 746391 0 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 373794584 42 0 0
T69 216471 0 0 0
T75 268842 0 0 0
T81 224345 0 0 0
T134 79911 5 0 0
T136 0 8 0 0
T137 0 8 0 0
T175 87330 0 0 0
T184 611380 0 0 0
T269 0 5 0 0
T270 0 8 0 0
T271 0 8 0 0
T272 247398 0 0 0
T273 141536 0 0 0
T274 103328 0 0 0
T275 746391 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 373794584 3922 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 373794584 3922 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 373794584 3922 0 0
T1 301011 4 0 0
T2 145559 1 0 0
T3 74838 1 0 0
T4 247113 1 0 0
T16 608791 12 0 0
T32 221084 2 0 0
T45 121858 2 0 0
T91 407722 1 0 0
T93 392002 1 0 0
T97 137592 2 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 373794584 3922 0 0
T1 301011 4 0 0
T2 145559 1 0 0
T3 74838 1 0 0
T4 247113 1 0 0
T16 608791 12 0 0
T32 221084 2 0 0
T45 121858 2 0 0
T91 407722 1 0 0
T93 392002 1 0 0
T97 137592 2 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%