Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T136,T270,T271
0	1	Covered	T136,T270,T271
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T136,T270,T271
1	Covered	T136,T270,T271

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T136,T270,T271
1	Covered	T136,T270,T271

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T136,T270,T271
1	1	Covered	T136,T270,T271

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T136,T270,T271
1	0	Covered	T136,T270,T271
1	1	Covered	T136,T270,T271

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T136,T270,T271

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T136,T270,T271
0	Covered	T136,T270,T271

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T136,T270,T271
0	Covered	T136,T270,T271

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	747589168	733664780	0	0
CheckNGreaterZero_A	1822	1822	0	0
GntImpliesReady_A	747589168	8454	0	0
GntImpliesValid_A	747589168	8454	0	0
GrantKnown_A	747589168	733664780	0	0
IdxKnown_A	747589168	733664780	0	0
IndexIsCorrect_A	747589168	8454	0	0
NoReadyValidNoGrant_A	747589168	0	0	0
Priority_A	747589168	8454	0	0
ReadyAndValidImplyGrant_A	747589168	8454	0	0
ReqAndReadyImplyGrant_A	747589168	8454	0	0
ReqImpliesValid_A	747589168	8454	0	0
ValidKnown_A	747589168	733664780	0	0
gen_data_port_assertion.DataFlow_A	747589168	8454	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747589168	733664780	0	0
T1	602022	601732	0	0
T2	291118	290994	0	0
T3	149676	149560	0	0
T4	494226	494000	0	0
T16	1217582	1216996	0	0
T32	442168	441948	0	0
T45	243716	243504	0	0
T91	815444	815342	0	0
T93	784004	783880	0	0
T97	275184	275074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1822	1822	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T16	2	2	0	0
T32	2	2	0	0
T45	2	2	0	0
T91	2	2	0	0
T93	2	2	0	0
T97	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747589168	8454	0	0
T38	260974	0	0	0
T136	163428	2819	0	0
T209	782188	0	0	0
T270	0	2818	0	0
T271	0	2817	0	0
T320	210002	0	0	0
T363	522074	0	0	0
T364	177954	0	0	0
T365	306376	0	0	0
T366	456284	0	0	0
T367	197052	0	0	0
T368	326306	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747589168	8454	0	0
T38	260974	0	0	0
T136	163428	2819	0	0
T209	782188	0	0	0
T270	0	2818	0	0
T271	0	2817	0	0
T320	210002	0	0	0
T363	522074	0	0	0
T364	177954	0	0	0
T365	306376	0	0	0
T366	456284	0	0	0
T367	197052	0	0	0
T368	326306	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747589168	733664780	0	0
T1	602022	601732	0	0
T2	291118	290994	0	0
T3	149676	149560	0	0
T4	494226	494000	0	0
T16	1217582	1216996	0	0
T32	442168	441948	0	0
T45	243716	243504	0	0
T91	815444	815342	0	0
T93	784004	783880	0	0
T97	275184	275074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747589168	733664780	0	0
T1	602022	601732	0	0
T2	291118	290994	0	0
T3	149676	149560	0	0
T4	494226	494000	0	0
T16	1217582	1216996	0	0
T32	442168	441948	0	0
T45	243716	243504	0	0
T91	815444	815342	0	0
T93	784004	783880	0	0
T97	275184	275074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747589168	8454	0	0
T38	260974	0	0	0
T136	163428	2819	0	0
T209	782188	0	0	0
T270	0	2818	0	0
T271	0	2817	0	0
T320	210002	0	0	0
T363	522074	0	0	0
T364	177954	0	0	0
T365	306376	0	0	0
T366	456284	0	0	0
T367	197052	0	0	0
T368	326306	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747589168	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747589168	8454	0	0
T38	260974	0	0	0
T136	163428	2819	0	0
T209	782188	0	0	0
T270	0	2818	0	0
T271	0	2817	0	0
T320	210002	0	0	0
T363	522074	0	0	0
T364	177954	0	0	0
T365	306376	0	0	0
T366	456284	0	0	0
T367	197052	0	0	0
T368	326306	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747589168	8454	0	0
T38	260974	0	0	0
T136	163428	2819	0	0
T209	782188	0	0	0
T270	0	2818	0	0
T271	0	2817	0	0
T320	210002	0	0	0
T363	522074	0	0	0
T364	177954	0	0	0
T365	306376	0	0	0
T366	456284	0	0	0
T367	197052	0	0	0
T368	326306	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747589168	8454	0	0
T38	260974	0	0	0
T136	163428	2819	0	0
T209	782188	0	0	0
T270	0	2818	0	0
T271	0	2817	0	0
T320	210002	0	0	0
T363	522074	0	0	0
T364	177954	0	0	0
T365	306376	0	0	0
T366	456284	0	0	0
T367	197052	0	0	0
T368	326306	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747589168	8454	0	0
T38	260974	0	0	0
T136	163428	2819	0	0
T209	782188	0	0	0
T270	0	2818	0	0
T271	0	2817	0	0
T320	210002	0	0	0
T363	522074	0	0	0
T364	177954	0	0	0
T365	306376	0	0	0
T366	456284	0	0	0
T367	197052	0	0	0
T368	326306	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747589168	733664780	0	0
T1	602022	601732	0	0
T2	291118	290994	0	0
T3	149676	149560	0	0
T4	494226	494000	0	0
T16	1217582	1216996	0	0
T32	442168	441948	0	0
T45	243716	243504	0	0
T91	815444	815342	0	0
T93	784004	783880	0	0
T97	275184	275074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747589168	8454	0	0
T38	260974	0	0	0
T136	163428	2819	0	0
T209	782188	0	0	0
T270	0	2818	0	0
T271	0	2817	0	0
T320	210002	0	0	0
T363	522074	0	0	0
T364	177954	0	0	0
T365	306376	0	0	0
T366	456284	0	0	0
T367	197052	0	0	0
T368	326306	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T136,T270,T271
0	1	Covered	T136,T270,T271
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T136,T270,T271
1	Covered	T136,T270,T271

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T136,T270,T271
1	Covered	T136,T270,T271

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T136,T270,T271
1	1	Covered	T136,T270,T271

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T136,T270,T271
1	0	Covered	T136,T270,T271
1	1	Covered	T136,T270,T271

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T136,T270,T271

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T136,T270,T271
0	Covered	T136,T270,T271

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T136,T270,T271
0	Covered	T136,T270,T271

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	373794584	366832390	0	0
CheckNGreaterZero_A	911	911	0	0
GntImpliesReady_A	373794584	5270	0	0
GntImpliesValid_A	373794584	5270	0	0
GrantKnown_A	373794584	366832390	0	0
IdxKnown_A	373794584	366832390	0	0
IndexIsCorrect_A	373794584	5270	0	0
NoReadyValidNoGrant_A	373794584	0	0	0
Priority_A	373794584	5270	0	0
ReadyAndValidImplyGrant_A	373794584	5270	0	0
ReqAndReadyImplyGrant_A	373794584	5270	0	0
ReqImpliesValid_A	373794584	5270	0	0
ValidKnown_A	373794584	366832390	0	0
gen_data_port_assertion.DataFlow_A	373794584	5270	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	366832390	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	911	911	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T32	1	1	0	0
T45	1	1	0	0
T91	1	1	0	0
T93	1	1	0	0
T97	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	5270	0	0
T38	130487	0	0	0
T136	81714	1758	0	0
T209	391094	0	0	0
T270	0	1756	0	0
T271	0	1756	0	0
T320	105001	0	0	0
T363	261037	0	0	0
T364	88977	0	0	0
T365	153188	0	0	0
T366	228142	0	0	0
T367	98526	0	0	0
T368	163153	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	5270	0	0
T38	130487	0	0	0
T136	81714	1758	0	0
T209	391094	0	0	0
T270	0	1756	0	0
T271	0	1756	0	0
T320	105001	0	0	0
T363	261037	0	0	0
T364	88977	0	0	0
T365	153188	0	0	0
T366	228142	0	0	0
T367	98526	0	0	0
T368	163153	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	366832390	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	366832390	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	5270	0	0
T38	130487	0	0	0
T136	81714	1758	0	0
T209	391094	0	0	0
T270	0	1756	0	0
T271	0	1756	0	0
T320	105001	0	0	0
T363	261037	0	0	0
T364	88977	0	0	0
T365	153188	0	0	0
T366	228142	0	0	0
T367	98526	0	0	0
T368	163153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	5270	0	0
T38	130487	0	0	0
T136	81714	1758	0	0
T209	391094	0	0	0
T270	0	1756	0	0
T271	0	1756	0	0
T320	105001	0	0	0
T363	261037	0	0	0
T364	88977	0	0	0
T365	153188	0	0	0
T366	228142	0	0	0
T367	98526	0	0	0
T368	163153	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	5270	0	0
T38	130487	0	0	0
T136	81714	1758	0	0
T209	391094	0	0	0
T270	0	1756	0	0
T271	0	1756	0	0
T320	105001	0	0	0
T363	261037	0	0	0
T364	88977	0	0	0
T365	153188	0	0	0
T366	228142	0	0	0
T367	98526	0	0	0
T368	163153	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	5270	0	0
T38	130487	0	0	0
T136	81714	1758	0	0
T209	391094	0	0	0
T270	0	1756	0	0
T271	0	1756	0	0
T320	105001	0	0	0
T363	261037	0	0	0
T364	88977	0	0	0
T365	153188	0	0	0
T366	228142	0	0	0
T367	98526	0	0	0
T368	163153	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	5270	0	0
T38	130487	0	0	0
T136	81714	1758	0	0
T209	391094	0	0	0
T270	0	1756	0	0
T271	0	1756	0	0
T320	105001	0	0	0
T363	261037	0	0	0
T364	88977	0	0	0
T365	153188	0	0	0
T366	228142	0	0	0
T367	98526	0	0	0
T368	163153	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	366832390	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	5270	0	0
T38	130487	0	0	0
T136	81714	1758	0	0
T209	391094	0	0	0
T270	0	1756	0	0
T271	0	1756	0	0
T320	105001	0	0	0
T363	261037	0	0	0
T364	88977	0	0	0
T365	153188	0	0	0
T366	228142	0	0	0
T367	98526	0	0	0
T368	163153	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T136,T270,T271
0	1	Covered	T136,T270,T271
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T136,T270,T271
1	Covered	T136,T270,T271

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T136,T270,T271
1	Covered	T136,T270,T271

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T136,T270,T271
1	1	Covered	T136,T270,T271

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T136,T270,T271
1	0	Covered	T136,T270,T271
1	1	Covered	T136,T270,T271

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T136,T270,T271

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T136,T270,T271
0	Covered	T136,T270,T271

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T136,T270,T271
0	Covered	T136,T270,T271

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	373794584	366832390	0	0
CheckNGreaterZero_A	911	911	0	0
GntImpliesReady_A	373794584	3184	0	0
GntImpliesValid_A	373794584	3184	0	0
GrantKnown_A	373794584	366832390	0	0
IdxKnown_A	373794584	366832390	0	0
IndexIsCorrect_A	373794584	3184	0	0
NoReadyValidNoGrant_A	373794584	0	0	0
Priority_A	373794584	3184	0	0
ReadyAndValidImplyGrant_A	373794584	3184	0	0
ReqAndReadyImplyGrant_A	373794584	3184	0	0
ReqImpliesValid_A	373794584	3184	0	0
ValidKnown_A	373794584	366832390	0	0
gen_data_port_assertion.DataFlow_A	373794584	3184	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	366832390	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	911	911	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T32	1	1	0	0
T45	1	1	0	0
T91	1	1	0	0
T93	1	1	0	0
T97	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	3184	0	0
T38	130487	0	0	0
T136	81714	1061	0	0
T209	391094	0	0	0
T270	0	1062	0	0
T271	0	1061	0	0
T320	105001	0	0	0
T363	261037	0	0	0
T364	88977	0	0	0
T365	153188	0	0	0
T366	228142	0	0	0
T367	98526	0	0	0
T368	163153	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	3184	0	0
T38	130487	0	0	0
T136	81714	1061	0	0
T209	391094	0	0	0
T270	0	1062	0	0
T271	0	1061	0	0
T320	105001	0	0	0
T363	261037	0	0	0
T364	88977	0	0	0
T365	153188	0	0	0
T366	228142	0	0	0
T367	98526	0	0	0
T368	163153	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	366832390	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	366832390	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	3184	0	0
T38	130487	0	0	0
T136	81714	1061	0	0
T209	391094	0	0	0
T270	0	1062	0	0
T271	0	1061	0	0
T320	105001	0	0	0
T363	261037	0	0	0
T364	88977	0	0	0
T365	153188	0	0	0
T366	228142	0	0	0
T367	98526	0	0	0
T368	163153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	3184	0	0
T38	130487	0	0	0
T136	81714	1061	0	0
T209	391094	0	0	0
T270	0	1062	0	0
T271	0	1061	0	0
T320	105001	0	0	0
T363	261037	0	0	0
T364	88977	0	0	0
T365	153188	0	0	0
T366	228142	0	0	0
T367	98526	0	0	0
T368	163153	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	3184	0	0
T38	130487	0	0	0
T136	81714	1061	0	0
T209	391094	0	0	0
T270	0	1062	0	0
T271	0	1061	0	0
T320	105001	0	0	0
T363	261037	0	0	0
T364	88977	0	0	0
T365	153188	0	0	0
T366	228142	0	0	0
T367	98526	0	0	0
T368	163153	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	3184	0	0
T38	130487	0	0	0
T136	81714	1061	0	0
T209	391094	0	0	0
T270	0	1062	0	0
T271	0	1061	0	0
T320	105001	0	0	0
T363	261037	0	0	0
T364	88977	0	0	0
T365	153188	0	0	0
T366	228142	0	0	0
T367	98526	0	0	0
T368	163153	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	3184	0	0
T38	130487	0	0	0
T136	81714	1061	0	0
T209	391094	0	0	0
T270	0	1062	0	0
T271	0	1061	0	0
T320	105001	0	0	0
T363	261037	0	0	0
T364	88977	0	0	0
T365	153188	0	0	0
T366	228142	0	0	0
T367	98526	0	0	0
T368	163153	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	366832390	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	3184	0	0
T38	130487	0	0	0
T136	81714	1061	0	0
T209	391094	0	0	0
T270	0	1062	0	0
T271	0	1061	0	0
T320	105001	0	0	0
T363	261037	0	0	0
T364	88977	0	0	0
T365	153188	0	0	0
T366	228142	0	0	0
T367	98526	0	0	0
T368	163153	0	0	0