Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3716524	1			T23	330		T24	2145		T25	257
values[2]	750117	1			T23	43		T25	39		T137	409
values[3]	109310	1			T25	2		T137	17		T318	17
values[4]	58287	1			T318	18		T550	12		T474	49
values[5]	40094	1			T318	17		T550	13		T474	23
values[6]	29657	1			T318	17		T550	12		T474	16
values[7]	23885	1			T318	18		T550	12		T474	30
values[8]	19935	1			T318	17		T550	12		T474	14
values[9]	17513	1			T318	17		T550	13		T474	2
values[10]	16125	1			T318	17		T550	12		T474	1
values[11]	15176	1			T318	18		T550	12		T474	4
values[12]	14473	1			T318	18		T550	12		T474	1
values[13]	13388	1			T318	17		T550	12		T474	2
values[14]	12693	1			T318	17		T550	12		T474	4
values[15]	11877	1			T318	18		T550	12		T474	2
values[16]	11790	1			T318	17		T550	12		T474	4
values[17]	11463	1			T318	17		T550	12		T474	4
values[18]	11033	1			T318	17		T550	12		T474	4
values[19]	10796	1			T318	17		T550	12		T474	3
values[20]	10323	1			T318	17		T550	14		T474	2
values[21]	10012	1			T318	17		T550	12		T474	1
values[22]	9547	1			T318	17		T550	12		T474	4
values[23]	9169	1			T318	18		T550	12		T474	3
values[24]	8934	1			T318	18		T550	12		T474	3
values[25]	8407	1			T318	17		T550	12		T474	3
values[26]	8234	1			T318	18		T550	12		T474	4
values[27]	8133	1			T318	17		T550	12		T474	2
values[28]	7822	1			T318	17		T550	12		T474	1
values[29]	7337	1			T318	17		T550	12		T474	1
values[30]	6602	1			T318	17		T550	12		T474	2
values[31]	6128	1			T318	17		T550	12		T474	3
values[32]	5623	1			T318	17		T550	13		T474	3
values[33]	5298	1			T318	17		T550	12		T474	1
values[34]	4904	1			T318	18		T550	12		T474	2
values[35]	4636	1			T318	17		T550	13		T474	2
values[36]	4510	1			T318	17		T550	12		T474	1
values[37]	4269	1			T318	17		T550	12		T474	1
values[38]	3870	1			T318	17		T550	12		T474	2
values[39]	3776	1			T318	18		T550	12		T474	1
values[40]	3695	1			T318	17		T550	12		T474	3
values[41]	3641	1			T318	17		T550	12		T474	4
values[42]	3562	1			T318	17		T550	12		T474	1
values[43]	3520	1			T318	17		T550	12		T474	2
values[44]	3400	1			T318	17		T550	12		T474	4
values[45]	3330	1			T318	19		T550	12		T474	3
values[46]	3223	1			T318	17		T550	12		T474	1
values[47]	3192	1			T318	18		T550	12		T474	2
values[48]	3181	1			T318	17		T550	12		T474	1
values[49]	3079	1			T318	18		T550	12		T474	2
values[50]	2940	1			T318	18		T550	12		T474	1
values[51]	2865	1			T318	19		T550	12		T474	1
values[52]	2781	1			T318	17		T550	12		T474	3
values[53]	2697	1			T318	18		T550	12		T474	2
values[54]	2708	1			T318	17		T550	12		T474	2
values[55]	2697	1			T318	17		T550	13		T474	1
values[56]	2637	1			T318	17		T550	12		T474	2
values[57]	2501	1			T318	17		T550	12		T474	4
values[58]	2512	1			T318	19		T550	13		T474	2
values[59]	2540	1			T318	17		T550	12		T474	2
values[60]	2520	1			T318	17		T550	13		T474	3
values[61]	2822	1			T318	18		T550	12		T474	1
values[62]	4616	1			T318	18		T550	13		T474	4
values[63]	17220	1			T318	165		T550	72		T474	17
values[64]	228244	1			T318	2896		T550	2158		T474	62

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4777209	1			T23	1406		T24	2224		T25	807
values[2]	802923	1			T23	170		T25	133		T137	356
values[3]	77945	1			T23	9		T25	17		T137	27
values[4]	14144	1			T137	6		T318	61		T451	2
values[5]	5253	1			T318	16		T550	25		T320	1
values[6]	3226	1			T318	6		T550	9		T320	1
values[7]	2658	1			T318	2		T550	3		T474	2
values[8]	2188	1			T318	2		T550	1		T474	1
values[9]	1945	1			T318	2		T550	1		T474	1
values[10]	1694	1			T318	2		T474	1		T475	5
values[11]	1477	1			T318	2		T474	1		T475	12
values[12]	1432	1			T318	2		T474	1		T475	10
values[13]	1431	1			T318	2		T474	1		T475	10
values[14]	1395	1			T318	2		T474	1		T475	11
values[15]	1296	1			T318	2		T474	2		T475	5
values[16]	1264	1			T318	2		T474	1		T475	9
values[17]	1164	1			T318	2		T474	2		T475	12
values[18]	1081	1			T318	2		T474	2		T475	2
values[19]	997	1			T318	2		T474	1		T475	1
values[20]	927	1			T318	2		T474	2		T464	1
values[21]	942	1			T318	2		T474	1		T464	1
values[22]	902	1			T318	2		T474	2		T464	1
values[23]	816	1			T318	2		T474	4		T464	1
values[24]	784	1			T318	2		T474	2		T464	1
values[25]	836	1			T318	2		T474	4		T464	1
values[26]	795	1			T318	2		T474	1		T464	1
values[27]	740	1			T318	2		T474	1		T464	1
values[28]	670	1			T318	2		T474	1		T464	1
values[29]	635	1			T318	2		T474	1		T464	1
values[30]	628	1			T318	2		T474	1		T464	1
values[31]	595	1			T318	2		T474	1		T464	1
values[32]	611	1			T318	2		T474	2		T464	1
values[33]	621	1			T318	2		T474	3		T464	1
values[34]	592	1			T318	2		T474	5		T464	1
values[35]	561	1			T318	2		T474	2		T464	1
values[36]	554	1			T318	2		T474	1		T464	1
values[37]	518	1			T318	2		T474	1		T464	1
values[38]	557	1			T318	2		T474	1		T464	1
values[39]	512	1			T318	3		T474	3		T464	1
values[40]	479	1			T318	2		T474	2		T464	1
values[41]	513	1			T318	2		T474	1		T464	1
values[42]	485	1			T318	2		T474	2		T464	1
values[43]	520	1			T318	2		T474	4		T464	1
values[44]	484	1			T318	2		T474	4		T464	1
values[45]	454	1			T318	2		T474	1		T464	1
values[46]	499	1			T318	2		T474	1		T464	1
values[47]	450	1			T318	2		T474	1		T464	1
values[48]	421	1			T318	2		T474	2		T464	1
values[49]	451	1			T318	2		T474	2		T464	1
values[50]	444	1			T318	2		T474	2		T464	1
values[51]	455	1			T318	2		T474	1		T464	1
values[52]	403	1			T318	2		T474	1		T464	1
values[53]	418	1			T318	2		T474	5		T464	1
values[54]	418	1			T318	2		T474	3		T464	1
values[55]	406	1			T318	2		T474	7		T464	1
values[56]	398	1			T318	2		T474	4		T464	1
values[57]	407	1			T318	2		T474	2		T464	1
values[58]	382	1			T318	2		T474	1		T464	1
values[59]	382	1			T318	2		T474	1		T464	1
values[60]	370	1			T318	2		T474	2		T464	1
values[61]	421	1			T318	2		T474	1		T464	1
values[62]	663	1			T318	2		T474	6		T464	1
values[63]	3102	1			T318	48		T474	48		T464	1
values[64]	27800	1			T318	370		T474	109		T464	217

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	565758	1			T23	143		T24	2288		T25	32
values[2]	2647346	1			T23	295		T25	234		T137	513
values[3]	1161811	1			T23	100		T25	83		T137	1469
values[4]	153118	1			T23	15		T25	3		T137	40
values[5]	79116	1			T23	16		T137	1		T318	17
values[6]	51946	1			T23	2		T318	17		T550	12
values[7]	37942	1			T23	4		T318	17		T550	12
values[8]	30071	1			T23	6		T318	17		T550	12
values[9]	24962	1			T23	3		T318	17		T550	12
values[10]	22024	1			T23	3		T318	17		T550	12
values[11]	19960	1			T318	17		T550	12		T474	3
values[12]	17997	1			T318	17		T550	12		T474	1
values[13]	16759	1			T318	17		T550	12		T474	5
values[14]	15924	1			T318	17		T550	12		T474	2
values[15]	15098	1			T318	17		T550	13		T474	5
values[16]	14447	1			T318	17		T550	12		T474	3
values[17]	13974	1			T318	18		T550	12		T474	3
values[18]	13698	1			T318	17		T550	12		T474	5
values[19]	13052	1			T318	17		T550	12		T474	2
values[20]	12210	1			T318	17		T550	13		T474	2
values[21]	11787	1			T318	17		T550	12		T474	3
values[22]	11474	1			T318	17		T550	12		T474	7
values[23]	10926	1			T318	17		T550	12		T474	1
values[24]	10667	1			T318	17		T550	12		T474	1
values[25]	10182	1			T318	17		T550	12		T474	1
values[26]	9731	1			T318	17		T550	12		T474	1
values[27]	9023	1			T318	18		T550	12		T474	1
values[28]	8568	1			T318	17		T550	12		T474	1
values[29]	7963	1			T318	17		T550	12		T474	2
values[30]	7428	1			T318	17		T550	12		T474	1
values[31]	7132	1			T318	18		T550	12		T474	1
values[32]	6713	1			T318	17		T550	12		T474	2
values[33]	5992	1			T318	17		T550	12		T474	1
values[34]	5605	1			T318	17		T550	12		T474	1
values[35]	5148	1			T318	17		T550	12		T474	1
values[36]	4876	1			T318	17		T550	12		T474	2
values[37]	4502	1			T318	17		T550	12		T474	2
values[38]	4341	1			T318	17		T550	12		T474	1
values[39]	4096	1			T318	17		T550	12		T474	1
values[40]	3899	1			T318	18		T550	12		T474	3
values[41]	3807	1			T318	17		T550	12		T474	2
values[42]	3671	1			T318	18		T550	12		T474	5
values[43]	3554	1			T318	18		T550	12		T474	1
values[44]	3547	1			T318	17		T550	12		T474	1
values[45]	3644	1			T318	17		T550	12		T474	1
values[46]	3607	1			T318	17		T550	12		T474	1
values[47]	3488	1			T318	17		T550	12		T474	2
values[48]	3459	1			T318	17		T550	12		T474	1
values[49]	3335	1			T318	17		T550	12		T474	2
values[50]	3236	1			T318	17		T550	12		T474	2
values[51]	3099	1			T318	17		T550	12		T474	1
values[52]	3118	1			T318	17		T550	12		T474	1
values[53]	3061	1			T318	17		T550	12		T474	1
values[54]	2982	1			T318	19		T550	12		T474	2
values[55]	2915	1			T318	17		T550	12		T474	1
values[56]	2975	1			T318	17		T550	12		T474	2
values[57]	2804	1			T318	17		T550	12		T474	1
values[58]	2836	1			T318	17		T550	12		T474	4
values[59]	2692	1			T318	18		T550	12		T474	3
values[60]	2604	1			T318	17		T550	12		T474	2
values[61]	2805	1			T318	17		T550	13		T474	5
values[62]	4135	1			T318	17		T550	12		T474	8
values[63]	19011	1			T318	20		T550	14		T474	22
values[64]	213627	1			T318	3227		T550	2116		T474	82