Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2197798	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32114045

1

T4

5013

T5

15168

T6

14646

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	23558382	1			T4	1947		T5	6760		T6	3945
values[0x0]	8959288	1			T4	3066		T5	8408		T6	10701
values[0x1]	1794173	1			T4	338		T5	1178		T6	469

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	554335	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

33757508

1

T4

5351

T5

16346

T6

15115

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16087235	1			T4	2676		T5	8174		T6	7559
valid_sources[0x01]	16087341	1			T4	2675		T5	8172		T6	7556
valid_sources[0x02]	33856	1			T11	1		T385	215		T401	345
valid_sources[0x03]	33629	1			T210	1		T385	205		T401	350
valid_sources[0x04]	34490	1			T209	1		T11	1		T385	188
valid_sources[0x05]	34076	1			T210	2		T385	209		T401	314
valid_sources[0x06]	34223	1			T385	196		T401	582		T563	21
valid_sources[0x07]	35103	1			T27	1		T11	1		T385	147
valid_sources[0x08]	34677	1			T385	182		T401	408		T568	5
valid_sources[0x09]	34963	1			T385	181		T401	294		T568	10
valid_sources[0x0a]	33792	1			T27	2		T209	1		T210	2
valid_sources[0x0b]	33844	1			T27	2		T209	4		T385	183
valid_sources[0x0c]	33586	1			T27	1		T11	2		T210	1
valid_sources[0x0d]	35244	1			T385	179		T401	399		T563	26
valid_sources[0x0e]	34154	1			T27	2		T11	1		T210	1
valid_sources[0x0f]	35035	1			T27	1		T11	1		T210	1
valid_sources[0x10]	35435	1			T209	1		T385	176		T401	438
valid_sources[0x11]	33382	1			T209	2		T210	1		T385	226
valid_sources[0x12]	34031	1			T11	1		T210	1		T385	186
valid_sources[0x13]	34288	1			T209	3		T11	1		T210	2
valid_sources[0x14]	34221	1			T385	197		T401	374		T563	30
valid_sources[0x15]	33948	1			T11	1		T210	1		T385	163
valid_sources[0x16]	34546	1			T27	1		T11	1		T385	183
valid_sources[0x17]	35916	1			T11	1		T385	216		T401	283
valid_sources[0x18]	34192	1			T385	206		T401	261		T563	14
valid_sources[0x19]	41476	1			T29	39		T210	2		T385	191
valid_sources[0x1a]	34029	1			T27	1		T385	162		T401	376
valid_sources[0x1b]	33668	1			T27	3		T209	1		T11	1
valid_sources[0x1c]	34094	1			T27	2		T209	1		T385	130
valid_sources[0x1d]	33389	1			T210	1		T385	231		T401	338
valid_sources[0x1e]	34531	1			T27	2		T385	138		T401	410
valid_sources[0x1f]	34582	1			T30	39		T209	1		T11	1
valid_sources[0x20]	34763	1			T210	1		T385	171		T401	358

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22942066

1

T4

1947

T5

6760

T6

3945

values[0x0]

all_enables

biggest_size

8920549

1

T4

3066

T5

8408

T6

10701

values[0x1]

all_enables

biggest_size

251430

1

T27

17

T29

17

T30

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2948386	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

465996

1

T23

54

T24

280

T25

38

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1155595	1			T23	115		T24	715		T25	98
values[0x0]	1102915	1			T23	132		T24	707		T25	89
values[0x1]	1155872	1			T23	118		T24	723		T25	105

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2282640	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1131742

1

T23

126

T24

706

T25

95

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53486	1			T23	5		T24	6		T25	2
valid_sources[0x01]	53774	1			T23	1		T24	36		T137	39
valid_sources[0x02]	53930	1			T23	1		T24	14		T25	7
valid_sources[0x03]	53881	1			T23	5		T24	33		T25	8
valid_sources[0x04]	53417	1			T23	9		T137	30		T535	26
valid_sources[0x05]	53360	1			T24	11		T25	9		T137	31
valid_sources[0x06]	53122	1			T23	3		T24	110		T25	2
valid_sources[0x07]	54305	1			T23	1		T24	46		T25	5
valid_sources[0x08]	52721	1			T23	13		T24	6		T25	18
valid_sources[0x09]	53613	1			T23	4		T24	27		T25	11
valid_sources[0x0a]	52688	1			T23	23		T24	58		T137	19
valid_sources[0x0b]	53450	1			T23	2		T24	39		T25	5
valid_sources[0x0c]	52530	1			T23	17		T24	26		T25	3
valid_sources[0x0d]	53305	1			T24	72		T25	4		T137	26
valid_sources[0x0e]	53024	1			T23	14		T25	2		T137	31
valid_sources[0x0f]	53255	1			T23	9		T24	65		T25	3
valid_sources[0x10]	53114	1			T23	1		T24	43		T25	5
valid_sources[0x11]	52953	1			T23	7		T24	73		T25	2
valid_sources[0x12]	53425	1			T23	2		T24	48		T25	1
valid_sources[0x13]	52779	1			T23	4		T24	45		T25	6
valid_sources[0x14]	54341	1			T23	12		T24	45		T25	3
valid_sources[0x15]	53838	1			T23	2		T24	62		T25	2
valid_sources[0x16]	52398	1			T23	2		T24	43		T25	2
valid_sources[0x17]	53459	1			T23	7		T24	18		T25	3
valid_sources[0x18]	54161	1			T23	2		T24	49		T25	4
valid_sources[0x19]	53696	1			T23	7		T24	22		T25	3
valid_sources[0x1a]	52424	1			T23	18		T25	2		T137	27
valid_sources[0x1b]	52746	1			T23	1		T24	5		T25	3
valid_sources[0x1c]	52410	1			T23	12		T24	54		T25	2
valid_sources[0x1d]	53035	1			T23	2		T24	65		T25	31
valid_sources[0x1e]	53686	1			T23	4		T24	11		T25	2
valid_sources[0x1f]	53571	1			T24	82		T25	5		T137	31
valid_sources[0x20]	53968	1			T23	1		T24	43		T137	34

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48533

1

T23

1

T24

29

T25

4

values[0x0]

all_enables

biggest_size

368955

1

T23

47

T24

223

T25

26

values[0x1]

all_enables

biggest_size

48508

1

T23

6

T24

28

T25

8

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3130918	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

509892

1

T23

232

T24

315

T25

126

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1247461	1			T23	542		T24	734		T25	306
values[0x0]	1150005	1			T23	511		T24	740		T25	329
values[0x1]	1243344	1			T23	527		T24	750		T25	319

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2403843	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1236967

1

T23

545

T24

735

T25

306

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56587	1			T23	40		T24	18		T25	15
valid_sources[0x01]	57426	1			T23	15		T24	48		T25	2
valid_sources[0x02]	57177	1			T23	15		T24	8		T25	9
valid_sources[0x03]	56994	1			T23	22		T24	42		T25	16
valid_sources[0x04]	56019	1			T23	29		T25	15		T137	30
valid_sources[0x05]	56997	1			T23	23		T24	17		T25	7
valid_sources[0x06]	56992	1			T23	36		T24	121		T25	4
valid_sources[0x07]	57469	1			T23	23		T24	34		T25	7
valid_sources[0x08]	55782	1			T23	30		T24	5		T25	48
valid_sources[0x09]	56876	1			T23	9		T24	30		T25	8
valid_sources[0x0a]	56759	1			T23	41		T24	43		T25	13
valid_sources[0x0b]	57159	1			T23	29		T24	34		T25	12
valid_sources[0x0c]	57327	1			T23	39		T24	21		T25	11
valid_sources[0x0d]	56966	1			T23	12		T24	65		T25	4
valid_sources[0x0e]	57310	1			T23	33		T25	16		T137	25
valid_sources[0x0f]	57387	1			T23	42		T24	67		T25	13
valid_sources[0x10]	56510	1			T23	19		T24	46		T25	16
valid_sources[0x11]	56671	1			T23	41		T24	76		T25	21
valid_sources[0x12]	57262	1			T23	28		T24	49		T25	7
valid_sources[0x13]	57054	1			T23	8		T24	28		T25	8
valid_sources[0x14]	57567	1			T23	41		T24	46		T25	13
valid_sources[0x15]	57486	1			T23	23		T24	53		T25	16
valid_sources[0x16]	56465	1			T23	17		T24	42		T25	15
valid_sources[0x17]	57378	1			T23	18		T24	22		T25	23
valid_sources[0x18]	57473	1			T23	29		T24	57		T25	10
valid_sources[0x19]	56888	1			T23	28		T24	45		T25	16
valid_sources[0x1a]	56849	1			T23	60		T25	18		T137	34
valid_sources[0x1b]	55446	1			T23	11		T24	5		T25	13
valid_sources[0x1c]	56275	1			T23	17		T24	42		T25	13
valid_sources[0x1d]	56866	1			T23	20		T24	58		T25	23
valid_sources[0x1e]	56972	1			T23	24		T24	25		T25	1
valid_sources[0x1f]	56547	1			T23	24		T24	41		T25	14
valid_sources[0x20]	56330	1			T23	13		T24	46		T25	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53258

1

T23

25

T24

34

T25

13

values[0x0]

all_enables

biggest_size

403308

1

T23

189

T24

254

T25

103

values[0x1]

all_enables

biggest_size

53326

1

T23

18

T24

27

T25

10

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2961091	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

468496

1

T23

88

T24

294

T25

49

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1161265	1			T23	191		T24	761		T25	107
values[0x0]	1108954	1			T23	183		T24	731		T25	112
values[0x1]	1159368	1			T23	199		T24	796		T25	126

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2293392	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1136195

1

T23

187

T24

745

T25

126

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53847	1			T23	16		T24	20		T25	3
valid_sources[0x01]	53755	1			T23	8		T24	51		T25	3
valid_sources[0x02]	54322	1			T23	3		T24	20		T25	5
valid_sources[0x03]	53088	1			T23	2		T24	42		T25	4
valid_sources[0x04]	53977	1			T23	19		T25	6		T137	12
valid_sources[0x05]	54373	1			T23	3		T24	7		T25	11
valid_sources[0x06]	54468	1			T23	5		T24	90		T25	7
valid_sources[0x07]	53315	1			T23	7		T24	48		T25	6
valid_sources[0x08]	52975	1			T23	14		T24	18		T25	23
valid_sources[0x09]	53894	1			T23	3		T24	21		T25	9
valid_sources[0x0a]	53055	1			T23	15		T24	55		T25	3
valid_sources[0x0b]	53520	1			T23	2		T24	32		T25	5
valid_sources[0x0c]	53431	1			T23	20		T24	35		T25	2
valid_sources[0x0d]	53552	1			T23	6		T24	59		T25	3
valid_sources[0x0e]	53274	1			T23	11		T25	11		T137	15
valid_sources[0x0f]	53305	1			T23	19		T24	65		T25	2
valid_sources[0x10]	54044	1			T23	15		T24	32		T25	5
valid_sources[0x11]	53122	1			T23	14		T24	51		T25	6
valid_sources[0x12]	53848	1			T23	5		T24	63		T25	4
valid_sources[0x13]	53371	1			T23	4		T24	41		T25	2
valid_sources[0x14]	54258	1			T23	24		T24	55		T25	5
valid_sources[0x15]	53389	1			T23	8		T24	60		T25	6
valid_sources[0x16]	53232	1			T23	3		T24	50		T25	3
valid_sources[0x17]	54986	1			T23	7		T24	39		T25	3
valid_sources[0x18]	53139	1			T23	3		T24	47		T25	6
valid_sources[0x19]	52968	1			T23	5		T24	34		T25	5
valid_sources[0x1a]	53499	1			T23	16		T25	4		T137	20
valid_sources[0x1b]	52981	1			T23	4		T24	9		T25	8
valid_sources[0x1c]	53366	1			T23	10		T24	32		T25	7
valid_sources[0x1d]	53645	1			T23	8		T24	53		T25	24
valid_sources[0x1e]	53699	1			T23	12		T24	32		T25	2
valid_sources[0x1f]	53756	1			T23	5		T24	64		T25	5
valid_sources[0x20]	53398	1			T23	10		T24	46		T25	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48961

1

T23

13

T24

29

T25

2

values[0x0]

all_enables

biggest_size

370660

1

T23

64

T24

237

T25

37

values[0x1]

all_enables

biggest_size

48875

1

T23

11

T24

28

T25

10