Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	401274637	46109081	0	0
DepthKnown_A	401274637	401183608	0	0
RvalidKnown_A	401274637	401183608	0	0
WreadyKnown_A	401274637	401183608	0	0
gen_passthru_fifo.paramCheckPass	926	926	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	46109081	0	0
T4	93640	10687	0	0
T5	249665	30924	0	0
T6	100839	28911	0	0
T17	152411	25112	0	0
T18	265023	33505	0	0
T19	160818	16424	0	0
T20	113222	124609	0	0
T51	268782	33831	0	0
T111	94323	11055	0	0
T112	70683	7151	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	401183608	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	401183608	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	401183608	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	401274637	37373750	0	0
DepthKnown_A	401274637	401183608	0	0
RvalidKnown_A	401274637	401183608	0	0
WreadyKnown_A	401274637	401183608	0	0
gen_passthru_fifo.paramCheckPass	926	926	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	37373750	0	0
T4	93640	8253	0	0
T5	249665	22129	0	0
T6	100839	20277	0	0
T17	152411	17484	0	0
T18	265023	24326	0	0
T19	160818	13030	0	0
T20	113222	108310	0	0
T51	268782	24732	0	0
T111	94323	8611	0	0
T112	70683	5329	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	401183608	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	401183608	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	401183608	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	401274637	37411118	0	0
DepthKnown_A	401274637	401183608	0	0
RvalidKnown_A	401274637	401183608	0	0
WreadyKnown_A	401274637	401183608	0	0
gen_passthru_fifo.paramCheckPass	926	926	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	37411118	0	0
T4	93640	5494	0	0
T5	249665	16706	0	0
T6	100839	15676	0	0
T17	152411	8679	0	0
T18	265023	18192	0	0
T19	160818	10286	0	0
T20	113222	165742	0	0
T51	268782	18493	0	0
T111	94323	6270	0	0
T112	70683	4236	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	401183608	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	401183608	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	401183608	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	401274637	32206890	0	0
DepthKnown_A	401274637	401183608	0	0
RvalidKnown_A	401274637	401183608	0	0
WreadyKnown_A	401274637	401183608	0	0
gen_passthru_fifo.paramCheckPass	926	926	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	32206890	0	0
T4	93640	5351	0	0
T5	249665	16346	0	0
T6	100839	15115	0	0
T17	152411	8405	0	0
T18	265023	17809	0	0
T19	160818	10061	0	0
T20	113222	101858	0	0
T51	268782	18110	0	0
T111	94323	6116	0	0
T112	70683	4121	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	401183608	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	401183608	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	401183608	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473998616	82040	0	0
DepthKnown_A	473998616	473895369	0	0
RvalidKnown_A	473998616	473895369	0	0
WreadyKnown_A	473998616	473895369	0	0
gen_passthru_fifo.paramCheckPass	2816	2816	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	82040	0	0
T4	93640	13	0	0
T5	249665	151	0	0
T6	100839	63	0	0
T17	152411	26	0	0
T18	265023	151	0	0
T19	160818	26	0	0
T20	113222	27	0	0
T51	268782	151	0	0
T111	94323	13	0	0
T112	70683	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2816	2816	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473998616	84298	0	0
DepthKnown_A	473998616	473895369	0	0
RvalidKnown_A	473998616	473895369	0	0
WreadyKnown_A	473998616	473895369	0	0
gen_passthru_fifo.paramCheckPass	2816	2816	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	84298	0	0
T4	93640	13	0	0
T5	249665	151	0	0
T6	100839	63	0	0
T17	152411	26	0	0
T18	265023	151	0	0
T19	160818	26	0	0
T20	113222	27	0	0
T51	268782	151	0	0
T111	94323	13	0	0
T112	70683	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2816	2816	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473998616	48132	0	0
DepthKnown_A	473998616	473895369	0	0
RvalidKnown_A	473998616	473895369	0	0
WreadyKnown_A	473998616	473895369	0	0
gen_passthru_fifo.paramCheckPass	2816	2816	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	48132	0	0
T4	93640	12	0	0
T5	249665	95	0	0
T6	100839	59	0	0
T17	152411	23	0	0
T18	265023	95	0	0
T19	160818	24	0	0
T20	113222	0	0	0
T21	0	5	0	0
T51	268782	95	0	0
T111	94323	12	0	0
T112	70683	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2816	2816	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473998616	48132	0	0
DepthKnown_A	473998616	473895369	0	0
RvalidKnown_A	473998616	473895369	0	0
WreadyKnown_A	473998616	473895369	0	0
gen_passthru_fifo.paramCheckPass	2816	2816	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	48132	0	0
T4	93640	12	0	0
T5	249665	95	0	0
T6	100839	59	0	0
T17	152411	23	0	0
T18	265023	95	0	0
T19	160818	24	0	0
T20	113222	0	0	0
T21	0	5	0	0
T51	268782	95	0	0
T111	94323	12	0	0
T112	70683	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2816	2816	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473998616	33908	0	0
DepthKnown_A	473998616	473895369	0	0
RvalidKnown_A	473998616	473895369	0	0
WreadyKnown_A	473998616	473895369	0	0
gen_passthru_fifo.paramCheckPass	2816	2816	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	33908	0	0
T4	93640	1	0	0
T5	249665	56	0	0
T6	100839	4	0	0
T17	152411	3	0	0
T18	265023	56	0	0
T19	160818	2	0	0
T20	113222	27	0	0
T51	268782	56	0	0
T111	94323	1	0	0
T112	70683	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2816	2816	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473998616	36166	0	0
DepthKnown_A	473998616	473895369	0	0
RvalidKnown_A	473998616	473895369	0	0
WreadyKnown_A	473998616	473895369	0	0
gen_passthru_fifo.paramCheckPass	2816	2816	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	36166	0	0
T4	93640	1	0	0
T5	249665	56	0	0
T6	100839	4	0	0
T17	152411	3	0	0
T18	265023	56	0	0
T19	160818	2	0	0
T20	113222	27	0	0
T51	268782	56	0	0
T111	94323	1	0	0
T112	70683	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473998616	473895369	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2816	2816	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0