Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.80 99.93 99.75 99.51 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 99.80 99.93 99.75 99.51 100.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL1528152799.93
ALWAYS684375.00
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CONT_ASSIGN1622711100.00
CONT_ASSIGN1624111100.00
CONT_ASSIGN1627511100.00
CONT_ASSIGN1628911100.00
ALWAYS16295199199100.00
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CONT_ASSIGN1732111100.00
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CONT_ASSIGN1732711100.00
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ALWAYS17634199199100.00
ALWAYS17837552552100.00
CONT_ASSIGN1899400
CONT_ASSIGN1900211100.00
CONT_ASSIGN1900311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 0 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
16227 1 1
16241 1 1
16275 1 1
16289 1 1
16295 1 1
16296 1 1
16297 1 1
16298 1 1
16299 1 1
16300 1 1
16301 1 1
16302 1 1
16303 1 1
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16305 1 1
16306 1 1
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16308 1 1
16309 1 1
16310 1 1
16311 1 1
16312 1 1
16313 1 1
16314 1 1
16315 1 1
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16317 1 1
16318 1 1
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16327 1 1
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16331 1 1
16332 1 1
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18964 1 1
18968 1 1
18972 1 1
18976 1 1
18980 1 1
18994 unreachable
19002 1 1
19003 1 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions1983197899.75
Logical1983197899.75
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-1648098.96
16481-16500100.00
16500100.00
16500-16993100.00
16996-1762899.74

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 204 203 99.51
TERNARY 16496 2 2 100.00
IF 68 3 2 66.67
CASE 17838 199 199 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16496 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T5,T17,T18
0 Covered T4,T5,T6


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Not Covered
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 17838 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T5,T17,T18
addr_hit[1] Covered T232,T233,T237
addr_hit[2] Covered T232,T233,T237
addr_hit[3] Covered T232,T233,T237
addr_hit[4] Covered T232,T233,T237
addr_hit[5] Covered T232,T233,T237
addr_hit[6] Covered T232,T233,T237
addr_hit[7] Covered T232,T233,T237
addr_hit[8] Covered T232,T233,T237
addr_hit[9] Covered T226,T128,T129
addr_hit[10] Covered T226,T128,T129
addr_hit[11] Covered T226,T128,T129
addr_hit[12] Covered T226,T128,T129
addr_hit[13] Covered T226,T128,T129
addr_hit[14] Covered T226,T128,T129
addr_hit[15] Covered T226,T128,T129
addr_hit[16] Covered T226,T128,T129
addr_hit[17] Covered T191,T192,T193
addr_hit[18] Covered T191,T192,T193
addr_hit[19] Covered T191,T192,T193
addr_hit[20] Covered T191,T192,T193
addr_hit[21] Covered T191,T192,T193
addr_hit[22] Covered T191,T192,T193
addr_hit[23] Covered T191,T192,T193
addr_hit[24] Covered T191,T192,T193
addr_hit[25] Covered T74,T75,T256
addr_hit[26] Covered T74,T75,T256
addr_hit[27] Covered T74,T75,T256
addr_hit[28] Covered T74,T75,T256
addr_hit[29] Covered T74,T75,T256
addr_hit[30] Covered T74,T75,T256
addr_hit[31] Covered T74,T75,T256
addr_hit[32] Covered T74,T75,T256
addr_hit[33] Covered T237,T83,T255
addr_hit[34] Covered T237,T83,T255
addr_hit[35] Covered T237,T83,T255
addr_hit[36] Covered T237,T83,T255
addr_hit[37] Covered T237,T83,T255
addr_hit[38] Covered T237,T83,T255
addr_hit[39] Covered T237,T83,T255
addr_hit[40] Covered T237,T83,T255
addr_hit[41] Covered T237,T83,T255
addr_hit[42] Covered T237,T83,T255
addr_hit[43] Covered T237,T83,T255
addr_hit[44] Covered T237,T83,T255
addr_hit[45] Covered T237,T83,T255
addr_hit[46] Covered T237,T83,T255
addr_hit[47] Covered T237,T83,T255
addr_hit[48] Covered T237,T83,T255
addr_hit[49] Covered T237,T83,T255
addr_hit[50] Covered T237,T83,T255
addr_hit[51] Covered T237,T83,T255
addr_hit[52] Covered T237,T83,T255
addr_hit[53] Covered T237,T83,T255
addr_hit[54] Covered T237,T83,T255
addr_hit[55] Covered T237,T83,T255
addr_hit[56] Covered T237,T83,T255
addr_hit[57] Covered T237,T83,T255
addr_hit[58] Covered T237,T83,T255
addr_hit[59] Covered T237,T83,T255
addr_hit[60] Covered T237,T83,T255
addr_hit[61] Covered T237,T83,T255
addr_hit[62] Covered T237,T83,T255
addr_hit[63] Covered T237,T83,T255
addr_hit[64] Covered T237,T83,T255
addr_hit[65] Covered T71,T72,T237
addr_hit[66] Covered T237,T95,T255
addr_hit[67] Covered T237,T95,T255
addr_hit[68] Covered T71,T72,T237
addr_hit[69] Covered T71,T72,T237
addr_hit[70] Covered T237,T95,T255
addr_hit[71] Covered T237,T255,T139
addr_hit[72] Covered T237,T255,T139
addr_hit[73] Covered T225,T237,T264
addr_hit[74] Covered T225,T237,T264
addr_hit[75] Covered T237,T255,T139
addr_hit[76] Covered T225,T237,T264
addr_hit[77] Covered T225,T237,T264
addr_hit[78] Covered T225,T237,T264
addr_hit[79] Covered T225,T237,T264
addr_hit[80] Covered T225,T237,T264
addr_hit[81] Covered T237,T255,T139
addr_hit[82] Covered T225,T237,T264
addr_hit[83] Covered T237,T255,T139
addr_hit[84] Covered T237,T255,T139
addr_hit[85] Covered T237,T255,T139
addr_hit[86] Covered T237,T255,T139
addr_hit[87] Covered T237,T255,T139
addr_hit[88] Covered T237,T255,T139
addr_hit[89] Covered T237,T255,T139
addr_hit[90] Covered T237,T255,T139
addr_hit[91] Covered T237,T255,T139
addr_hit[92] Covered T237,T255,T139
addr_hit[93] Covered T237,T255,T139
addr_hit[94] Covered T237,T255,T139
addr_hit[95] Covered T237,T255,T139
addr_hit[96] Covered T237,T255,T139
addr_hit[97] Covered T237,T255,T139
addr_hit[98] Covered T237,T255,T139
addr_hit[99] Covered T237,T255,T139
addr_hit[100] Covered T237,T255,T139
addr_hit[101] Covered T237,T255,T139
addr_hit[102] Covered T237,T255,T139
addr_hit[103] Covered T237,T272,T255
addr_hit[104] Covered T237,T272,T255
addr_hit[105] Covered T237,T255,T139
addr_hit[106] Covered T237,T272,T255
addr_hit[107] Covered T237,T272,T255
addr_hit[108] Covered T237,T272,T255
addr_hit[109] Covered T237,T272,T255
addr_hit[110] Covered T237,T272,T255
addr_hit[111] Covered T237,T255,T139
addr_hit[112] Covered T229,T237,T272
addr_hit[113] Covered T229,T237,T255
addr_hit[114] Covered T237,T255,T139
addr_hit[115] Covered T229,T237,T255
addr_hit[116] Covered T229,T237,T255
addr_hit[117] Covered T229,T237,T255
addr_hit[118] Covered T237,T255,T139
addr_hit[119] Covered T237,T255,T139
addr_hit[120] Covered T237,T255,T139
addr_hit[121] Covered T237,T255,T139
addr_hit[122] Covered T237,T255,T139
addr_hit[123] Covered T5,T18,T51
addr_hit[124] Covered T5,T18,T51
addr_hit[125] Covered T5,T18,T51
addr_hit[126] Covered T5,T18,T51
addr_hit[127] Covered T71,T72,T237
addr_hit[128] Covered T71,T72,T237
addr_hit[129] Covered T237,T255,T139
addr_hit[130] Covered T237,T255,T139
addr_hit[131] Covered T237,T255,T139
addr_hit[132] Covered T237,T255,T139
addr_hit[133] Covered T237,T255,T139
addr_hit[134] Covered T237,T255,T139
addr_hit[135] Covered T237,T255,T139
addr_hit[136] Covered T237,T255,T139
addr_hit[137] Covered T237,T255,T139
addr_hit[138] Covered T237,T255,T139
addr_hit[139] Covered T237,T255,T139
addr_hit[140] Covered T237,T255,T139
addr_hit[141] Covered T237,T255,T139
addr_hit[142] Covered T237,T255,T139
addr_hit[143] Covered T237,T255,T139
addr_hit[144] Covered T237,T255,T139
addr_hit[145] Covered T237,T255,T139
addr_hit[146] Covered T237,T255,T139
addr_hit[147] Covered T237,T255,T139
addr_hit[148] Covered T237,T255,T139
addr_hit[149] Covered T17,T238,T279
addr_hit[150] Covered T215,T237,T216
addr_hit[151] Covered T148,T154,T155
addr_hit[152] Covered T5,T18,T51
addr_hit[153] Covered T5,T18,T51
addr_hit[154] Covered T237,T255,T139
addr_hit[155] Covered T237,T255,T139
addr_hit[156] Covered T258,T259,T261
addr_hit[157] Covered T258,T259,T261
addr_hit[158] Covered T258,T259,T261
addr_hit[159] Covered T258,T259,T261
addr_hit[160] Covered T258,T259,T261
addr_hit[161] Covered T237,T255,T139
addr_hit[162] Covered T237,T293,T294
addr_hit[163] Covered T237,T293,T294
addr_hit[164] Covered T237,T255,T139
addr_hit[165] Covered T237,T255,T139
addr_hit[166] Covered T237,T255,T139
addr_hit[167] Covered T237,T255,T139
addr_hit[168] Covered T135,T276,T237
addr_hit[169] Covered T237,T255,T139
addr_hit[170] Covered T237,T255,T139
addr_hit[171] Covered T163,T237,T255
addr_hit[172] Covered T237,T255,T139
addr_hit[173] Covered T237,T255,T139
addr_hit[174] Covered T237,T255,T139
addr_hit[175] Covered T237,T255,T139
addr_hit[176] Covered T237,T255,T139
addr_hit[177] Covered T237,T255,T139
addr_hit[178] Covered T163,T237,T255
addr_hit[179] Covered T237,T255,T139
addr_hit[180] Covered T163,T237,T255
addr_hit[181] Covered T237,T255,T139
addr_hit[182] Covered T209,T568,T563
addr_hit[183] Covered T209,T568,T563
addr_hit[184] Covered T209,T568,T563
addr_hit[185] Covered T209,T568,T563
addr_hit[186] Covered T457,T209,T700
addr_hit[187] Covered T209,T568,T563
addr_hit[188] Covered T191,T232,T74
addr_hit[189] Covered T74,T75,T256
addr_hit[190] Covered T71,T72,T225
addr_hit[191] Covered T5,T18,T51
addr_hit[192] Covered T5,T17,T18
addr_hit[193] Covered T163,T135,T258
addr_hit[194] Covered T5,T17,T18
addr_hit[195] Covered T5,T17,T18
addr_hit[196] Covered T239,T209,T240
addr_hit[197] Covered T209,T34,T100
default Covered T23,T24,T25


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 473998616 209471 0 0
reAfterRv 473998616 209471 0 0
rePulse 473998616 141512 0 0
wePulse 473998616 67959 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 473998616 209471 0 0
T5 249665 44 0 0
T6 100839 0 0 0
T17 152411 8 0 0
T18 265023 44 0 0
T19 160818 0 0 0
T20 113222 0 0 0
T21 124314 0 0 0
T50 0 44 0 0
T51 268782 44 0 0
T65 0 44 0 0
T71 0 39 0 0
T111 94323 0 0 0
T112 70683 0 0 0
T202 0 104 0 0
T238 0 8 0 0
T285 0 44 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 473998616 209471 0 0
T5 249665 44 0 0
T6 100839 0 0 0
T17 152411 8 0 0
T18 265023 44 0 0
T19 160818 0 0 0
T20 113222 0 0 0
T21 124314 0 0 0
T50 0 44 0 0
T51 268782 44 0 0
T65 0 44 0 0
T71 0 39 0 0
T111 94323 0 0 0
T112 70683 0 0 0
T202 0 104 0 0
T238 0 8 0 0
T285 0 44 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 473998616 141512 0 0
T5 249665 14 0 0
T6 100839 0 0 0
T17 152411 3 0 0
T18 265023 14 0 0
T19 160818 0 0 0
T20 113222 0 0 0
T21 124314 0 0 0
T50 0 14 0 0
T51 268782 14 0 0
T65 0 14 0 0
T71 0 17 0 0
T111 94323 0 0 0
T112 70683 0 0 0
T202 0 32 0 0
T238 0 3 0 0
T285 0 14 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 473998616 67959 0 0
T5 249665 30 0 0
T6 100839 0 0 0
T17 152411 5 0 0
T18 265023 30 0 0
T19 160818 0 0 0
T20 113222 0 0 0
T21 124314 0 0 0
T50 0 30 0 0
T51 268782 30 0 0
T65 0 30 0 0
T71 0 22 0 0
T111 94323 0 0 0
T112 70683 0 0 0
T202 0 72 0 0
T238 0 5 0 0
T285 0 30 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%