Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_por_aon_n_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T6,T71,T194
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T71,T72,T89
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T6,T71,T194

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	24764	24454	0	0
selKnown1	28807	27601	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	24764	24454	0	0
T26	1	0	0	0
T27	2	1	0	0
T38	1	0	0	0
T39	1	0	0	0
T40	1	0	0	0
T41	11	10	0	0
T43	1	0	0	0
T64	24	23	0	0
T68	1	0	0	0
T70	1	0	0	0
T71	3040	3038	0	0
T72	3831	3829	0	0
T73	135	133	0	0
T82	0	31	0	0
T83	0	3	0	0
T86	15	13	0	0
T87	5	5	0	0
T88	0	16	0	0
T91	0	3	0	0
T99	2	1	0	0
T107	0	2	0	0
T108	40	39	0	0
T195	0	23	0	0
T196	0	58	0	0
T197	3399	3397	0	0
T198	4436	4434	0	0
T199	2334	2332	0	0
T200	2075	2073	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	28807	27601	0	0
T5	2	1	0	0
T6	3	2	0	0
T17	1	0	0	0
T18	2	1	0	0
T19	2	1	0	0
T20	2	1	0	0
T21	1	0	0	0
T36	0	1	0	0
T51	2	1	0	0
T65	0	1	0	0
T86	22	20	0	0
T87	49	47	0	0
T88	9	17	0	0
T89	545	544	0	0
T91	32	61	0	0
T111	1	0	0	0
T112	1	0	0	0
T201	0	1	0	0
T202	0	4	0	0
T203	6	12	0	0
T204	18	35	0	0
T205	12	29	0	0
T206	9	17	0	0
T207	9	8	0	0
T208	15	14	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T71,T72,T89
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	1257	1237	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257	1237	0	0
T68	1	0	0	0
T70	1	0	0	0
T86	11	10	0	0
T87	28	27	0	0
T88	0	9	0	0
T89	545	544	0	0
T90	545	544	0	0
T91	0	30	0	0
T197	1	0	0	0
T198	1	0	0	0
T199	1	0	0	0
T200	1	0	0	0
T203	0	7	0	0
T204	0	18	0	0
T205	0	18	0	0
T206	0	9	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T89,T68,T69
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	147	132	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	147	132	0	0
T86	11	10	0	0
T87	21	20	0	0
T88	9	8	0	0
T91	32	31	0	0
T203	6	5	0	0
T204	18	17	0	0
T205	12	11	0	0
T206	9	8	0	0
T207	9	8	0	0
T208	15	14	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T89,T68,T73
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	179	164	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	179	164	0	0
T68	1	0	0	0
T69	1	0	0	0
T73	1	0	0	0
T86	8	7	0	0
T87	23	22	0	0
T88	15	14	0	0
T89	2	1	0	0
T90	2	1	0	0
T91	16	15	0	0
T203	5	4	0	0
T204	0	33	0	0
T205	0	26	0	0
T206	0	9	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T89,T68,T69
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	142	127	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	142	127	0	0
T86	10	9	0	0
T87	24	23	0	0
T88	13	12	0	0
T91	18	17	0	0
T203	5	4	0	0
T204	16	15	0	0
T205	15	14	0	0
T206	7	6	0	0
T207	8	7	0	0
T208	21	20	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T86,T87,T88
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	182	172	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	182	172	0	0
T86	14	13	0	0
T87	20	19	0	0
T88	18	17	0	0
T91	33	32	0	0
T203	7	6	0	0
T204	18	17	0	0
T205	35	34	0	0
T206	9	8	0	0
T207	12	11	0	0
T208	16	15	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T86,T87,T88
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	147	137	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	147	137	0	0
T86	9	8	0	0
T87	17	16	0	0
T88	19	18	0	0
T91	30	29	0	0
T203	5	4	0	0
T204	12	11	0	0
T205	25	24	0	0
T206	11	10	0	0
T207	4	3	0	0
T208	15	14	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T42,T64,T108
0	1	Covered	T42,T64,T108
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T42,T64,T108
1	1	Covered	T42,T64,T108

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	668	605	0	0
selKnown1	1474	558	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	668	605	0	0
T26	1	0	0	0
T27	2	1	0	0
T38	1	0	0	0
T39	1	0	0	0
T40	1	0	0	0
T41	11	10	0	0
T43	1	0	0	0
T64	24	23	0	0
T82	0	31	0	0
T83	0	3	0	0
T99	2	1	0	0
T107	0	2	0	0
T108	40	39	0	0
T195	0	23	0	0
T196	0	58	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474	558	0	0
T5	2	1	0	0
T6	3	2	0	0
T17	1	0	0	0
T18	2	1	0	0
T19	2	1	0	0
T20	2	1	0	0
T21	1	0	0	0
T36	0	1	0	0
T51	2	1	0	0
T65	0	1	0	0
T111	1	0	0	0
T112	1	0	0	0
T201	0	1	0	0
T202	0	4	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T71,T72,T73
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T89,T68,T90
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T71,T72,T73

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	19089	19072	0	0
selKnown1	471	458	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	19089	19072	0	0
T71	2965	2964	0	0
T72	3815	3814	0	0
T73	134	133	0	0
T86	8	7	0	0
T87	5	4	0	0
T88	16	15	0	0
T197	3383	3382	0	0
T198	4417	4416	0	0
T199	2258	2257	0	0
T200	2001	2000	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	471	458	0	0
T68	1	0	0	0
T86	10	9	0	0
T87	17	16	0	0
T88	9	8	0	0
T89	157	156	0	0
T90	157	156	0	0
T91	28	27	0	0
T203	6	5	0	0
T204	26	25	0	0
T205	23	22	0	0
T206	0	6	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T71,T72,T68
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T89,T68,T69
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T71,T72,T68

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	313	295	0	0
selKnown1	139	125	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	313	295	0	0
T68	1	0	0	0
T70	1	0	0	0
T71	75	74	0	0
T72	16	15	0	0
T73	1	0	0	0
T86	7	6	0	0
T87	0	1	0	0
T88	0	1	0	0
T91	0	3	0	0
T197	16	15	0	0
T198	19	18	0	0
T199	76	75	0	0
T200	74	73	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	139	125	0	0
T86	16	15	0	0
T87	14	13	0	0
T88	8	7	0	0
T91	22	21	0	0
T203	11	10	0	0
T204	16	15	0	0
T205	19	18	0	0
T206	9	8	0	0
T207	2	1	0	0
T208	18	17	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T27,T89,T69
0	1	Covered	T89,T68,T73
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T68,T69,T70
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T27,T89,T69
1	1	Covered	T89,T68,T73

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1329	1308	0	0
selKnown1	54	33	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329	1308	0	0
T11	1	0	0	0
T29	1	0	0	0
T30	1	0	0	0
T68	1	0	0	0
T70	1	0	0	0
T73	1	0	0	0
T86	0	22	0	0
T87	0	24	0	0
T88	0	18	0	0
T89	546	545	0	0
T90	546	545	0	0
T91	0	44	0	0
T203	0	10	0	0
T204	0	30	0	0
T205	0	19	0	0
T206	0	23	0	0
T209	1	0	0	0
T210	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	54	33	0	0
T68	2	1	0	0
T69	2	1	0	0
T70	2	1	0	0
T77	1	0	0	0
T80	1	0	0	0
T81	1	0	0	0
T86	0	3	0	0
T87	0	3	0	0
T88	0	3	0	0
T91	0	3	0	0
T102	1	0	0	0
T203	0	3	0	0
T204	0	3	0	0
T205	0	3	0	0
T211	1	0	0	0
T212	1	0	0	0
T213	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T27,T89,T69
0	1	Covered	T89,T68,T73
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T68,T69,T70
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T27,T89,T69
1	1	Covered	T89,T68,T73

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1325	1304	0	0
selKnown1	54	33	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1325	1304	0	0
T11	1	0	0	0
T29	1	0	0	0
T30	1	0	0	0
T68	1	0	0	0
T70	1	0	0	0
T73	1	0	0	0
T86	0	21	0	0
T87	0	22	0	0
T88	0	17	0	0
T89	546	545	0	0
T90	546	545	0	0
T91	0	45	0	0
T203	0	11	0	0
T204	0	31	0	0
T205	0	20	0	0
T206	0	22	0	0
T209	1	0	0	0
T210	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	54	33	0	0
T68	2	1	0	0
T69	2	1	0	0
T70	2	1	0	0
T77	1	0	0	0
T80	1	0	0	0
T81	1	0	0	0
T86	0	3	0	0
T87	0	3	0	0
T88	0	3	0	0
T91	0	3	0	0
T102	1	0	0	0
T203	0	3	0	0
T204	0	3	0	0
T205	0	3	0	0
T211	1	0	0	0
T212	1	0	0	0
T213	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T27,T89,T29
0	1	Covered	T71,T72,T89
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T68,T69,T70
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T27,T89,T29
1	1	Covered	T71,T72,T89

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	180	153	0	0
selKnown1	24	3	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	180	153	0	0
T11	1	0	0	0
T29	1	0	0	0
T30	1	0	0	0
T68	1	0	0	0
T69	1	0	0	0
T73	1	0	0	0
T86	0	15	0	0
T87	0	25	0	0
T88	0	12	0	0
T89	2	1	0	0
T90	0	1	0	0
T91	0	16	0	0
T197	1	0	0	0
T198	1	0	0	0
T203	0	13	0	0
T204	0	18	0	0
T205	0	18	0	0
T206	0	10	0	0
T209	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	24	3	0	0
T68	2	1	0	0
T69	2	1	0	0
T70	2	1	0	0
T77	1	0	0	0
T80	1	0	0	0
T81	1	0	0	0
T102	1	0	0	0
T211	1	0	0	0
T212	1	0	0	0
T213	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T27,T89,T29
0	1	Covered	T71,T72,T89
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T68,T69,T70
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T27,T89,T29
1	1	Covered	T71,T72,T89

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	178	151	0	0
selKnown1	24	3	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	178	151	0	0
T11	1	0	0	0
T29	1	0	0	0
T30	1	0	0	0
T68	1	0	0	0
T69	1	0	0	0
T73	1	0	0	0
T86	0	13	0	0
T87	0	26	0	0
T88	0	13	0	0
T89	2	1	0	0
T90	0	1	0	0
T91	0	17	0	0
T197	1	0	0	0
T198	1	0	0	0
T203	0	13	0	0
T204	0	17	0	0
T205	0	18	0	0
T206	0	10	0	0
T209	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	24	3	0	0
T68	2	1	0	0
T69	2	1	0	0
T70	2	1	0	0
T77	1	0	0	0
T80	1	0	0	0
T81	1	0	0	0
T102	1	0	0	0
T211	1	0	0	0
T212	1	0	0	0
T213	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T27,T68,T69
0	1	Covered	T68,T69,T70
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T68,T69,T70
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T27,T68,T69
1	1	Covered	T68,T69,T70

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	219	200	0	0
selKnown1	24	3	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	219	200	0	0
T86	11	10	0	0
T87	33	32	0	0
T88	26	25	0	0
T91	34	33	0	0
T203	8	7	0	0
T204	24	23	0	0
T205	20	19	0	0
T206	17	16	0	0
T207	19	18	0	0
T208	18	17	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	24	3	0	0
T68	2	1	0	0
T69	2	1	0	0
T70	2	1	0	0
T77	1	0	0	0
T80	1	0	0	0
T81	1	0	0	0
T102	1	0	0	0
T211	1	0	0	0
T212	1	0	0	0
T213	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T27,T68,T69
0	1	Covered	T68,T69,T70
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T68,T69,T70
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T27,T68,T69
1	1	Covered	T68,T69,T70

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	217	198	0	0
selKnown1	24	3	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	217	198	0	0
T86	10	9	0	0
T87	31	30	0	0
T88	25	24	0	0
T91	36	35	0	0
T203	8	7	0	0
T204	23	22	0	0
T205	20	19	0	0
T206	17	16	0	0
T207	21	20	0	0
T208	17	16	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	24	3	0	0
T68	2	1	0	0
T69	2	1	0	0
T70	2	1	0	0
T77	1	0	0	0
T80	1	0	0	0
T81	1	0	0	0
T102	1	0	0	0
T211	1	0	0	0
T212	1	0	0	0
T213	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T194,T214
0	1	Covered	T6,T71,T194
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T71,T72,T89
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T6,T194,T214
1	1	Covered	T6,T71,T194

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	622	583	0	0
selKnown1	12233	12207	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	622	583	0	0
T6	2	1	0	0
T27	1	0	0	0
T68	1	0	0	0
T71	1	0	0	0
T72	1	0	0	0
T78	1	0	0	0
T79	0	1	0	0
T89	149	148	0	0
T90	0	151	0	0
T194	2	1	0	0
T214	2	1	0	0
T215	33	32	0	0
T216	0	28	0	0
T217	0	1	0	0
T218	0	31	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	12233	12207	0	0
T27	1	0	0	0
T29	1	0	0	0
T30	1	0	0	0
T69	1	0	0	0
T71	1843	1842	0	0
T72	3774	3773	0	0
T73	130	129	0	0
T86	0	4	0	0
T87	0	6	0	0
T88	0	20	0	0
T89	1	0	0	0
T197	3316	3315	0	0
T198	0	56	0	0
T199	0	1529	0	0
T200	0	1464	0	0
T209	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T194,T214
0	1	Covered	T6,T71,T194
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T71,T72,T89
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T6,T194,T214
1	1	Covered	T6,T71,T194

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	624	585	0	0
selKnown1	12232	12206	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	624	585	0	0
T6	2	1	0	0
T27	1	0	0	0
T68	1	0	0	0
T71	1	0	0	0
T72	1	0	0	0
T78	1	0	0	0
T79	0	1	0	0
T89	149	148	0	0
T90	0	151	0	0
T194	2	1	0	0
T214	2	1	0	0
T215	33	32	0	0
T216	0	28	0	0
T217	0	1	0	0
T218	0	31	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	12232	12206	0	0
T27	1	0	0	0
T29	1	0	0	0
T30	1	0	0	0
T69	1	0	0	0
T71	1843	1842	0	0
T72	3774	3773	0	0
T73	130	129	0	0
T86	0	4	0	0
T87	0	7	0	0
T88	0	18	0	0
T89	1	0	0	0
T197	3316	3315	0	0
T198	0	56	0	0
T199	0	1529	0	0
T200	0	1464	0	0
T209	1	0	0	0