Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T152,T11,T308
0	1	Covered	T152,T308,T309
1	0	Covered	T11

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T152,T11,T308
1	Covered	T152,T11,T308

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T152,T11,T308
1	Covered	T152,T11,T308

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T152,T308,T309
1	1	Covered	T152,T11,T308

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T152,T11,T308
1	0	Covered	T152,T11,T308
1	1	Covered	T152,T308,T309

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T152,T11,T308

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T152,T11,T308
0	Covered	T152,T11,T308

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T152,T11,T308
0	Covered	T152,T11,T308

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	802549274	784975148	0	0
CheckNGreaterZero_A	1852	1852	0	0
GntImpliesReady_A	802549274	8464	0	0
GntImpliesValid_A	802549274	8464	0	0
GrantKnown_A	802549274	784975148	0	0
IdxKnown_A	802549274	784975148	0	0
IndexIsCorrect_A	802549274	8464	0	0
NoReadyValidNoGrant_A	802549274	0	0	0
Priority_A	802549274	8464	0	0
ReadyAndValidImplyGrant_A	802549274	8464	0	0
ReqAndReadyImplyGrant_A	802549274	8464	0	0
ReqImpliesValid_A	802549274	8464	0	0
ValidKnown_A	802549274	784975148	0	0
gen_data_port_assertion.DataFlow_A	802549274	8464	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802549274	784975148	0	0
T4	187280	187164	0	0
T5	499330	499126	0	0
T6	201678	201624	0	0
T17	304822	304706	0	0
T18	530046	529820	0	0
T19	321636	321388	0	0
T20	226444	226424	0	0
T51	537564	537338	0	0
T111	188646	188530	0	0
T112	141366	141250	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1852	1852	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0
T51	2	2	0	0
T111	2	2	0	0
T112	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802549274	8464	0	0
T45	1049576	0	0	0
T152	193818	2821	0	0
T153	200814	0	0	0
T308	0	2820	0	0
T309	0	2823	0	0
T311	490356	0	0	0
T406	544190	0	0	0
T407	449408	0	0	0
T408	494988	0	0	0
T409	426268	0	0	0
T410	328076	0	0	0
T411	301134	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802549274	8464	0	0
T45	1049576	0	0	0
T152	193818	2821	0	0
T153	200814	0	0	0
T308	0	2820	0	0
T309	0	2823	0	0
T311	490356	0	0	0
T406	544190	0	0	0
T407	449408	0	0	0
T408	494988	0	0	0
T409	426268	0	0	0
T410	328076	0	0	0
T411	301134	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802549274	784975148	0	0
T4	187280	187164	0	0
T5	499330	499126	0	0
T6	201678	201624	0	0
T17	304822	304706	0	0
T18	530046	529820	0	0
T19	321636	321388	0	0
T20	226444	226424	0	0
T51	537564	537338	0	0
T111	188646	188530	0	0
T112	141366	141250	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802549274	784975148	0	0
T4	187280	187164	0	0
T5	499330	499126	0	0
T6	201678	201624	0	0
T17	304822	304706	0	0
T18	530046	529820	0	0
T19	321636	321388	0	0
T20	226444	226424	0	0
T51	537564	537338	0	0
T111	188646	188530	0	0
T112	141366	141250	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802549274	8464	0	0
T45	1049576	0	0	0
T152	193818	2821	0	0
T153	200814	0	0	0
T308	0	2820	0	0
T309	0	2823	0	0
T311	490356	0	0	0
T406	544190	0	0	0
T407	449408	0	0	0
T408	494988	0	0	0
T409	426268	0	0	0
T410	328076	0	0	0
T411	301134	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802549274	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802549274	8464	0	0
T45	1049576	0	0	0
T152	193818	2821	0	0
T153	200814	0	0	0
T308	0	2820	0	0
T309	0	2823	0	0
T311	490356	0	0	0
T406	544190	0	0	0
T407	449408	0	0	0
T408	494988	0	0	0
T409	426268	0	0	0
T410	328076	0	0	0
T411	301134	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802549274	8464	0	0
T45	1049576	0	0	0
T152	193818	2821	0	0
T153	200814	0	0	0
T308	0	2820	0	0
T309	0	2823	0	0
T311	490356	0	0	0
T406	544190	0	0	0
T407	449408	0	0	0
T408	494988	0	0	0
T409	426268	0	0	0
T410	328076	0	0	0
T411	301134	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802549274	8464	0	0
T45	1049576	0	0	0
T152	193818	2821	0	0
T153	200814	0	0	0
T308	0	2820	0	0
T309	0	2823	0	0
T311	490356	0	0	0
T406	544190	0	0	0
T407	449408	0	0	0
T408	494988	0	0	0
T409	426268	0	0	0
T410	328076	0	0	0
T411	301134	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802549274	8464	0	0
T45	1049576	0	0	0
T152	193818	2821	0	0
T153	200814	0	0	0
T308	0	2820	0	0
T309	0	2823	0	0
T311	490356	0	0	0
T406	544190	0	0	0
T407	449408	0	0	0
T408	494988	0	0	0
T409	426268	0	0	0
T410	328076	0	0	0
T411	301134	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802549274	784975148	0	0
T4	187280	187164	0	0
T5	499330	499126	0	0
T6	201678	201624	0	0
T17	304822	304706	0	0
T18	530046	529820	0	0
T19	321636	321388	0	0
T20	226444	226424	0	0
T51	537564	537338	0	0
T111	188646	188530	0	0
T112	141366	141250	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802549274	8464	0	0
T45	1049576	0	0	0
T152	193818	2821	0	0
T153	200814	0	0	0
T308	0	2820	0	0
T309	0	2823	0	0
T311	490356	0	0	0
T406	544190	0	0	0
T407	449408	0	0	0
T408	494988	0	0	0
T409	426268	0	0	0
T410	328076	0	0	0
T411	301134	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T152,T11,T308
0	1	Covered	T152,T308,T309
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T152,T308,T309
1	Covered	T152,T11,T308

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T152,T308,T309
1	Covered	T152,T11,T308

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T152,T308,T309
1	1	Covered	T152,T308,T309

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T152,T11,T308
1	0	Covered	T152,T308,T309
1	1	Covered	T152,T308,T309

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T152,T308,T309

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T152,T11,T308
0	Covered	T152,T308,T309

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T152,T11,T308
0	Covered	T152,T308,T309

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401274637	392487574	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	401274637	5278	0	0
GntImpliesValid_A	401274637	5278	0	0
GrantKnown_A	401274637	392487574	0	0
IdxKnown_A	401274637	392487574	0	0
IndexIsCorrect_A	401274637	5278	0	0
NoReadyValidNoGrant_A	401274637	0	0	0
Priority_A	401274637	5278	0	0
ReadyAndValidImplyGrant_A	401274637	5278	0	0
ReqAndReadyImplyGrant_A	401274637	5278	0	0
ReqImpliesValid_A	401274637	5278	0	0
ValidKnown_A	401274637	392487574	0	0
gen_data_port_assertion.DataFlow_A	401274637	5278	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	392487574	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	5278	0	0
T45	524788	0	0	0
T152	96909	1758	0	0
T153	100407	0	0	0
T308	0	1758	0	0
T309	0	1762	0	0
T311	245178	0	0	0
T406	272095	0	0	0
T407	224704	0	0	0
T408	247494	0	0	0
T409	213134	0	0	0
T410	164038	0	0	0
T411	150567	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	5278	0	0
T45	524788	0	0	0
T152	96909	1758	0	0
T153	100407	0	0	0
T308	0	1758	0	0
T309	0	1762	0	0
T311	245178	0	0	0
T406	272095	0	0	0
T407	224704	0	0	0
T408	247494	0	0	0
T409	213134	0	0	0
T410	164038	0	0	0
T411	150567	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	392487574	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	392487574	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	5278	0	0
T45	524788	0	0	0
T152	96909	1758	0	0
T153	100407	0	0	0
T308	0	1758	0	0
T309	0	1762	0	0
T311	245178	0	0	0
T406	272095	0	0	0
T407	224704	0	0	0
T408	247494	0	0	0
T409	213134	0	0	0
T410	164038	0	0	0
T411	150567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	5278	0	0
T45	524788	0	0	0
T152	96909	1758	0	0
T153	100407	0	0	0
T308	0	1758	0	0
T309	0	1762	0	0
T311	245178	0	0	0
T406	272095	0	0	0
T407	224704	0	0	0
T408	247494	0	0	0
T409	213134	0	0	0
T410	164038	0	0	0
T411	150567	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	5278	0	0
T45	524788	0	0	0
T152	96909	1758	0	0
T153	100407	0	0	0
T308	0	1758	0	0
T309	0	1762	0	0
T311	245178	0	0	0
T406	272095	0	0	0
T407	224704	0	0	0
T408	247494	0	0	0
T409	213134	0	0	0
T410	164038	0	0	0
T411	150567	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	5278	0	0
T45	524788	0	0	0
T152	96909	1758	0	0
T153	100407	0	0	0
T308	0	1758	0	0
T309	0	1762	0	0
T311	245178	0	0	0
T406	272095	0	0	0
T407	224704	0	0	0
T408	247494	0	0	0
T409	213134	0	0	0
T410	164038	0	0	0
T411	150567	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	5278	0	0
T45	524788	0	0	0
T152	96909	1758	0	0
T153	100407	0	0	0
T308	0	1758	0	0
T309	0	1762	0	0
T311	245178	0	0	0
T406	272095	0	0	0
T407	224704	0	0	0
T408	247494	0	0	0
T409	213134	0	0	0
T410	164038	0	0	0
T411	150567	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	392487574	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	5278	0	0
T45	524788	0	0	0
T152	96909	1758	0	0
T153	100407	0	0	0
T308	0	1758	0	0
T309	0	1762	0	0
T311	245178	0	0	0
T406	272095	0	0	0
T407	224704	0	0	0
T408	247494	0	0	0
T409	213134	0	0	0
T410	164038	0	0	0
T411	150567	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T152,T11,T308
0	1	Covered	T152,T308,T309
1	0	Covered	T11

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T152,T11,T308
1	Covered	T152,T11,T308

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T152,T11,T308
1	Covered	T152,T11,T308

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T152,T308,T309
1	1	Covered	T152,T11,T308

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T152,T11,T308
1	0	Covered	T152,T11,T308
1	1	Covered	T152,T308,T309

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T152,T11,T308

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T152,T11,T308
0	Covered	T152,T11,T308

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T152,T11,T308
0	Covered	T152,T11,T308

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401274637	392487574	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	401274637	3186	0	0
GntImpliesValid_A	401274637	3186	0	0
GrantKnown_A	401274637	392487574	0	0
IdxKnown_A	401274637	392487574	0	0
IndexIsCorrect_A	401274637	3186	0	0
NoReadyValidNoGrant_A	401274637	0	0	0
Priority_A	401274637	3186	0	0
ReadyAndValidImplyGrant_A	401274637	3186	0	0
ReqAndReadyImplyGrant_A	401274637	3186	0	0
ReqImpliesValid_A	401274637	3186	0	0
ValidKnown_A	401274637	392487574	0	0
gen_data_port_assertion.DataFlow_A	401274637	3186	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	392487574	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	3186	0	0
T45	524788	0	0	0
T152	96909	1063	0	0
T153	100407	0	0	0
T308	0	1062	0	0
T309	0	1061	0	0
T311	245178	0	0	0
T406	272095	0	0	0
T407	224704	0	0	0
T408	247494	0	0	0
T409	213134	0	0	0
T410	164038	0	0	0
T411	150567	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	3186	0	0
T45	524788	0	0	0
T152	96909	1063	0	0
T153	100407	0	0	0
T308	0	1062	0	0
T309	0	1061	0	0
T311	245178	0	0	0
T406	272095	0	0	0
T407	224704	0	0	0
T408	247494	0	0	0
T409	213134	0	0	0
T410	164038	0	0	0
T411	150567	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	392487574	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	392487574	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	3186	0	0
T45	524788	0	0	0
T152	96909	1063	0	0
T153	100407	0	0	0
T308	0	1062	0	0
T309	0	1061	0	0
T311	245178	0	0	0
T406	272095	0	0	0
T407	224704	0	0	0
T408	247494	0	0	0
T409	213134	0	0	0
T410	164038	0	0	0
T411	150567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	3186	0	0
T45	524788	0	0	0
T152	96909	1063	0	0
T153	100407	0	0	0
T308	0	1062	0	0
T309	0	1061	0	0
T311	245178	0	0	0
T406	272095	0	0	0
T407	224704	0	0	0
T408	247494	0	0	0
T409	213134	0	0	0
T410	164038	0	0	0
T411	150567	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	3186	0	0
T45	524788	0	0	0
T152	96909	1063	0	0
T153	100407	0	0	0
T308	0	1062	0	0
T309	0	1061	0	0
T311	245178	0	0	0
T406	272095	0	0	0
T407	224704	0	0	0
T408	247494	0	0	0
T409	213134	0	0	0
T410	164038	0	0	0
T411	150567	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	3186	0	0
T45	524788	0	0	0
T152	96909	1063	0	0
T153	100407	0	0	0
T308	0	1062	0	0
T309	0	1061	0	0
T311	245178	0	0	0
T406	272095	0	0	0
T407	224704	0	0	0
T408	247494	0	0	0
T409	213134	0	0	0
T410	164038	0	0	0
T411	150567	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	3186	0	0
T45	524788	0	0	0
T152	96909	1063	0	0
T153	100407	0	0	0
T308	0	1062	0	0
T309	0	1061	0	0
T311	245178	0	0	0
T406	272095	0	0	0
T407	224704	0	0	0
T408	247494	0	0	0
T409	213134	0	0	0
T410	164038	0	0	0
T411	150567	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	392487574	0	0
T4	93640	93582	0	0
T5	249665	249563	0	0
T6	100839	100812	0	0
T17	152411	152353	0	0
T18	265023	264910	0	0
T19	160818	160694	0	0
T20	113222	113212	0	0
T51	268782	268669	0	0
T111	94323	94265	0	0
T112	70683	70625	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	3186	0	0
T45	524788	0	0	0
T152	96909	1063	0	0
T153	100407	0	0	0
T308	0	1062	0	0
T309	0	1061	0	0
T311	245178	0	0	0
T406	272095	0	0	0
T407	224704	0	0	0
T408	247494	0	0	0
T409	213134	0	0	0
T410	164038	0	0	0
T411	150567	0	0	0