Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1459751	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30261598

1

T4

16036

T5

3896

T6

13790

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	21753176	1			T4	7404		T5	1021		T6	5770
values[0x0]	8507667	1			T4	8632		T5	2875		T6	8020
values[0x1]	1460506	1			T4	1320		T5	97		T6	978

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9636	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

31711713

1

T4

17356

T5

3993

T6

14768

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15846117	1			T4	8678		T5	1997		T6	7385
valid_sources[0x01]	15845221	1			T4	8678		T5	1996		T6	7383
valid_sources[0x02]	386	1			T1	2		T200	1		T23	16
valid_sources[0x03]	447	1			T1	1		T24	61		T112	61
valid_sources[0x04]	407	1			T1	2		T23	7		T24	54
valid_sources[0x05]	421	1			T200	1		T24	68		T112	72
valid_sources[0x06]	425	1			T24	47		T112	72		T243	40
valid_sources[0x07]	396	1			T1	1		T24	53		T112	60
valid_sources[0x08]	3093	1			T24	75		T25	2673		T112	45
valid_sources[0x09]	419	1			T200	5		T24	57		T112	71
valid_sources[0x0a]	2085	1			T1	2		T200	1		T23	1723
valid_sources[0x0b]	373	1			T23	1		T24	30		T112	58
valid_sources[0x0c]	374	1			T1	1		T24	39		T112	50
valid_sources[0x0d]	425	1			T1	1		T200	1		T24	76
valid_sources[0x0e]	405	1			T24	40		T112	52		T243	56
valid_sources[0x0f]	370	1			T200	2		T24	41		T112	60
valid_sources[0x10]	560	1			T200	1		T23	134		T24	42
valid_sources[0x11]	423	1			T24	84		T112	46		T243	64
valid_sources[0x12]	419	1			T24	60		T112	52		T243	57
valid_sources[0x13]	347	1			T1	3		T24	31		T112	51
valid_sources[0x14]	412	1			T200	1		T24	54		T112	56
valid_sources[0x15]	400	1			T200	1		T24	46		T25	16
valid_sources[0x16]	443	1			T24	63		T25	16		T112	50
valid_sources[0x17]	416	1			T1	1		T200	1		T24	41
valid_sources[0x18]	368	1			T24	31		T112	63		T243	39
valid_sources[0x19]	422	1			T200	1		T24	59		T112	58
valid_sources[0x1a]	359	1			T200	2		T24	23		T112	52
valid_sources[0x1b]	486	1			T152	15		T24	51		T25	16
valid_sources[0x1c]	414	1			T200	1		T189	39		T24	32
valid_sources[0x1d]	431	1			T24	73		T112	45		T243	61
valid_sources[0x1e]	405	1			T1	1		T24	57		T112	49
valid_sources[0x1f]	416	1			T1	1		T24	24		T112	48
valid_sources[0x20]	396	1			T1	3		T24	43		T112	60

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21753176

1

T4

7404

T5

1021

T6

5770

values[0x0]

all_enables

biggest_size

8502790

1

T4

8632

T5

2875

T6

8020

values[0x1]

all_enables

biggest_size

5632

1

T21

22

T22

17

T1

16