| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 87.73 | 89.80 | 79.12 | 85.50 | 91.49 | 96.47 | 83.99 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 40.73 | 40.73 | 44.91 | 44.91 | 43.10 | 43.10 | 31.71 | 31.71 | 58.01 | 58.01 | 59.44 | 59.44 | 7.24 | 7.24 | /workspace/coverage/default/12.chip_sw_all_escalation_resets.2640567666 | ||
| 51.43 | 10.70 | 53.78 | 8.87 | 52.86 | 9.76 | 35.81 | 4.10 | 66.69 | 8.68 | 85.84 | 26.40 | 13.60 | 6.36 | /workspace/coverage/default/0.chip_jtag_csr_rw.2479444655 | ||
| 60.36 | 8.93 | 53.94 | 0.16 | 53.04 | 0.18 | 40.59 | 4.78 | 66.73 | 0.04 | 86.01 | 0.17 | 61.84 | 48.25 | /workspace/coverage/default/1.chip_sw_alert_test.3588610024 | ||
| 65.49 | 5.13 | 64.39 | 10.44 | 58.73 | 5.68 | 44.82 | 4.23 | 69.79 | 3.06 | 88.99 | 2.97 | 66.23 | 4.39 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1179128982 | ||
| 70.03 | 4.54 | 74.69 | 10.30 | 65.37 | 6.64 | 46.08 | 1.25 | 78.84 | 9.05 | 88.99 | 0.00 | 66.23 | 0.00 | /workspace/coverage/default/1.chip_plic_all_irqs_20.1589354567 | ||
| 72.66 | 2.63 | 74.69 | 0.01 | 65.39 | 0.03 | 61.62 | 15.54 | 78.86 | 0.02 | 89.16 | 0.17 | 66.23 | 0.00 | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3241802195 | ||
| 74.36 | 1.71 | 76.70 | 2.00 | 67.54 | 2.14 | 66.01 | 4.39 | 80.38 | 1.52 | 89.34 | 0.17 | 66.23 | 0.00 | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.99953214 | ||
| 75.92 | 1.56 | 79.08 | 2.38 | 70.37 | 2.83 | 66.30 | 0.29 | 83.52 | 3.14 | 90.03 | 0.70 | 66.23 | 0.00 | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2479178414 | ||
| 77.25 | 1.33 | 81.46 | 2.39 | 72.44 | 2.07 | 67.44 | 1.14 | 85.90 | 2.38 | 90.03 | 0.00 | 66.23 | 0.00 | /workspace/coverage/default/1.chip_plic_all_irqs_0.1638076386 | ||
| 77.98 | 0.73 | 81.67 | 0.21 | 72.56 | 0.12 | 67.49 | 0.04 | 86.04 | 0.14 | 93.88 | 3.85 | 66.23 | 0.00 | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3176080191 | ||
| 78.60 | 0.62 | 81.67 | 0.00 | 72.56 | 0.00 | 71.21 | 3.72 | 86.04 | 0.00 | 93.88 | 0.00 | 66.23 | 0.00 | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.4028345075 | ||
| 79.21 | 0.61 | 82.89 | 1.22 | 73.17 | 0.61 | 71.57 | 0.36 | 86.63 | 0.60 | 94.76 | 0.87 | 66.23 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3564223971 | ||
| 79.78 | 0.57 | 83.93 | 1.04 | 74.10 | 0.93 | 72.11 | 0.54 | 87.34 | 0.71 | 94.76 | 0.00 | 66.45 | 0.22 | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.198383560 | ||
| 80.35 | 0.57 | 84.73 | 0.79 | 74.86 | 0.76 | 72.56 | 0.45 | 88.21 | 0.87 | 95.28 | 0.52 | 66.45 | 0.00 | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1559610615 | ||
| 80.88 | 0.54 | 84.76 | 0.03 | 74.86 | 0.00 | 75.74 | 3.18 | 88.21 | 0.00 | 95.28 | 0.00 | 66.45 | 0.00 | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3808703662 | ||
| 81.30 | 0.42 | 85.34 | 0.58 | 75.37 | 0.51 | 76.66 | 0.92 | 88.73 | 0.52 | 95.28 | 0.00 | 66.45 | 0.00 | /workspace/coverage/default/2.chip_plic_all_irqs_10.292677182 | ||
| 81.68 | 0.37 | 86.07 | 0.73 | 75.93 | 0.56 | 76.76 | 0.10 | 89.58 | 0.85 | 95.28 | 0.00 | 66.45 | 0.00 | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.228265464 | ||
| 81.98 | 0.30 | 86.10 | 0.03 | 75.96 | 0.02 | 76.80 | 0.04 | 89.59 | 0.02 | 95.45 | 0.17 | 67.98 | 1.54 | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3819266958 | ||
| 82.28 | 0.30 | 86.72 | 0.63 | 76.39 | 0.43 | 77.24 | 0.44 | 89.89 | 0.30 | 95.45 | 0.00 | 67.98 | 0.00 | /workspace/coverage/default/1.chip_sw_gpio.183193704 | ||
| 82.54 | 0.26 | 86.72 | 0.00 | 76.39 | 0.00 | 77.91 | 0.66 | 89.89 | 0.00 | 95.45 | 0.00 | 68.86 | 0.88 | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2367188065 | ||
| 82.76 | 0.23 | 86.74 | 0.02 | 76.43 | 0.05 | 79.15 | 1.24 | 89.94 | 0.05 | 95.45 | 0.00 | 68.86 | 0.00 | /workspace/coverage/default/35.chip_sw_all_escalation_resets.2701757325 | ||
| 82.98 | 0.22 | 86.75 | 0.01 | 76.44 | 0.01 | 80.44 | 1.29 | 89.94 | 0.00 | 95.45 | 0.00 | 68.86 | 0.00 | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1212926203 | ||
| 83.19 | 0.21 | 86.76 | 0.01 | 76.45 | 0.02 | 81.49 | 1.05 | 89.94 | 0.00 | 95.63 | 0.17 | 68.86 | 0.00 | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1483387664 | ||
| 83.36 | 0.17 | 87.12 | 0.36 | 76.78 | 0.32 | 81.85 | 0.36 | 89.94 | 0.00 | 95.63 | 0.00 | 68.86 | 0.00 | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.352663898 | ||
| 83.51 | 0.14 | 87.65 | 0.54 | 76.88 | 0.11 | 82.05 | 0.20 | 89.97 | 0.02 | 95.63 | 0.00 | 68.86 | 0.00 | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.737350060 | ||
| 83.64 | 0.13 | 87.73 | 0.08 | 77.21 | 0.32 | 82.09 | 0.04 | 90.32 | 0.35 | 95.63 | 0.00 | 68.86 | 0.00 | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.353583785 | ||
| 83.77 | 0.13 | 87.96 | 0.23 | 77.40 | 0.19 | 82.11 | 0.01 | 90.64 | 0.32 | 95.63 | 0.00 | 68.86 | 0.00 | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1373308094 | ||
| 83.89 | 0.13 | 87.96 | 0.00 | 77.40 | 0.01 | 82.85 | 0.75 | 90.64 | 0.00 | 95.63 | 0.00 | 68.86 | 0.00 | /workspace/coverage/default/2.chip_sw_flash_init.1756194540 | ||
| 84.02 | 0.12 | 88.13 | 0.17 | 77.44 | 0.04 | 83.13 | 0.28 | 90.68 | 0.04 | 95.63 | 0.00 | 69.08 | 0.22 | /workspace/coverage/default/24.chip_sw_all_escalation_resets.1336540031 | ||
| 84.11 | 0.10 | 88.28 | 0.15 | 77.56 | 0.12 | 83.32 | 0.19 | 90.80 | 0.12 | 95.63 | 0.00 | 69.08 | 0.00 | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2558018787 | ||
| 84.20 | 0.09 | 88.34 | 0.06 | 77.96 | 0.40 | 83.32 | 0.00 | 90.90 | 0.10 | 95.63 | 0.00 | 69.08 | 0.00 | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1423998406 | ||
| 84.29 | 0.08 | 88.34 | 0.01 | 77.96 | 0.00 | 83.60 | 0.28 | 90.90 | 0.00 | 95.63 | 0.00 | 69.30 | 0.22 | /workspace/coverage/default/2.rom_e2e_shutdown_output.3547862333 | ||
| 84.37 | 0.08 | 88.37 | 0.03 | 78.01 | 0.04 | 83.61 | 0.01 | 90.93 | 0.03 | 95.80 | 0.17 | 69.52 | 0.22 | /workspace/coverage/default/44.chip_sw_all_escalation_resets.4021779248 | ||
| 84.45 | 0.07 | 88.38 | 0.01 | 78.02 | 0.01 | 83.61 | 0.00 | 90.96 | 0.02 | 95.98 | 0.17 | 69.74 | 0.22 | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2313799865 | ||
| 84.52 | 0.07 | 88.38 | 0.01 | 78.03 | 0.01 | 83.61 | 0.01 | 90.97 | 0.01 | 96.15 | 0.17 | 69.96 | 0.22 | /workspace/coverage/default/92.chip_sw_all_escalation_resets.2969102578 | ||
| 84.59 | 0.07 | 88.38 | 0.01 | 78.04 | 0.01 | 83.62 | 0.01 | 90.97 | 0.01 | 96.33 | 0.17 | 70.18 | 0.22 | /workspace/coverage/default/13.chip_sw_all_escalation_resets.1595700628 | ||
| 84.65 | 0.06 | 88.51 | 0.13 | 78.17 | 0.12 | 83.62 | 0.00 | 91.09 | 0.11 | 96.33 | 0.00 | 70.18 | 0.00 | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1088440900 | ||
| 84.70 | 0.05 | 88.51 | 0.00 | 78.17 | 0.00 | 83.72 | 0.10 | 91.09 | 0.00 | 96.33 | 0.00 | 70.39 | 0.22 | /workspace/coverage/default/61.chip_sw_all_escalation_resets.3470888143 | ||
| 84.75 | 0.05 | 88.51 | 0.00 | 78.17 | 0.00 | 83.79 | 0.07 | 91.09 | 0.00 | 96.33 | 0.00 | 70.61 | 0.22 | /workspace/coverage/default/29.chip_sw_all_escalation_resets.1144700054 | ||
| 84.80 | 0.04 | 88.52 | 0.01 | 78.18 | 0.01 | 83.82 | 0.03 | 91.10 | 0.01 | 96.33 | 0.00 | 70.83 | 0.22 | /workspace/coverage/default/31.chip_sw_all_escalation_resets.1383436473 | ||
| 84.84 | 0.04 | 88.54 | 0.03 | 78.22 | 0.04 | 83.98 | 0.16 | 91.13 | 0.03 | 96.33 | 0.00 | 70.83 | 0.00 | /workspace/coverage/default/1.chip_jtag_csr_rw.1866991224 | ||
| 84.88 | 0.04 | 88.67 | 0.12 | 78.22 | 0.00 | 84.08 | 0.10 | 91.15 | 0.02 | 96.33 | 0.00 | 70.83 | 0.00 | /workspace/coverage/default/2.chip_tap_straps_testunlock0.1005635038 | ||
| 84.92 | 0.04 | 88.67 | 0.00 | 78.22 | 0.00 | 84.10 | 0.01 | 91.15 | 0.00 | 96.33 | 0.00 | 71.05 | 0.22 | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.273244767 | ||
| 84.96 | 0.04 | 88.67 | 0.00 | 78.22 | 0.00 | 84.11 | 0.01 | 91.15 | 0.00 | 96.33 | 0.00 | 71.27 | 0.22 | /workspace/coverage/default/25.chip_sw_all_escalation_resets.439488077 | ||
| 84.99 | 0.04 | 88.67 | 0.00 | 78.22 | 0.00 | 84.11 | 0.01 | 91.15 | 0.00 | 96.33 | 0.00 | 71.49 | 0.22 | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1038650482 | ||
| 85.03 | 0.04 | 88.67 | 0.00 | 78.23 | 0.01 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 71.71 | 0.22 | /workspace/coverage/default/27.chip_sw_all_escalation_resets.1477112709 | ||
| 85.07 | 0.04 | 88.67 | 0.00 | 78.23 | 0.01 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 71.93 | 0.22 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2747463726 | ||
| 85.11 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.01 | 91.15 | 0.00 | 96.33 | 0.00 | 72.15 | 0.22 | /workspace/coverage/default/89.chip_sw_all_escalation_resets.650271702 | ||
| 85.14 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.01 | 91.15 | 0.00 | 96.33 | 0.00 | 72.37 | 0.22 | /workspace/coverage/default/36.chip_sw_all_escalation_resets.3714133140 | ||
| 85.18 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 72.59 | 0.22 | /workspace/coverage/default/0.chip_sw_all_escalation_resets.839660300 | ||
| 85.22 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 72.81 | 0.22 | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3943865287 | ||
| 85.25 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 73.03 | 0.22 | /workspace/coverage/default/10.chip_sw_all_escalation_resets.1287739787 | ||
| 85.29 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 73.25 | 0.22 | /workspace/coverage/default/11.chip_sw_all_escalation_resets.1922174011 | ||
| 85.32 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 73.46 | 0.22 | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1747199171 | ||
| 85.36 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 73.68 | 0.22 | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.370213612 | ||
| 85.40 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 73.90 | 0.22 | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2811089405 | ||
| 85.43 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 74.12 | 0.22 | /workspace/coverage/default/16.chip_sw_all_escalation_resets.4283475820 | ||
| 85.47 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 74.34 | 0.22 | /workspace/coverage/default/17.chip_sw_all_escalation_resets.3470434539 | ||
| 85.51 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 74.56 | 0.22 | /workspace/coverage/default/18.chip_sw_all_escalation_resets.1109056640 | ||
| 85.54 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 74.78 | 0.22 | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.248632491 | ||
| 85.58 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 75.00 | 0.22 | /workspace/coverage/default/19.chip_sw_all_escalation_resets.2984133815 | ||
| 85.62 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 75.22 | 0.22 | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2621887231 | ||
| 85.65 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 75.44 | 0.22 | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1310337916 | ||
| 85.69 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 75.66 | 0.22 | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3309782914 | ||
| 85.73 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 75.88 | 0.22 | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2706989573 | ||
| 85.76 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 76.10 | 0.22 | /workspace/coverage/default/23.chip_sw_all_escalation_resets.2261268989 | ||
| 85.80 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 76.32 | 0.22 | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1455250440 | ||
| 85.84 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 76.54 | 0.22 | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1363611918 | ||
| 85.87 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 76.75 | 0.22 | /workspace/coverage/default/26.chip_sw_all_escalation_resets.3230267239 | ||
| 85.91 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 76.97 | 0.22 | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1095998311 | ||
| 85.95 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 77.19 | 0.22 | /workspace/coverage/default/28.chip_sw_all_escalation_resets.822242996 | ||
| 85.98 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 77.41 | 0.22 | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3202451319 | ||
| 86.02 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 77.63 | 0.22 | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2621337513 | ||
| 86.06 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 77.85 | 0.22 | /workspace/coverage/default/33.chip_sw_all_escalation_resets.5832250 | ||
| 86.09 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 78.07 | 0.22 | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1048965234 | ||
| 86.13 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 78.29 | 0.22 | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.171243824 | ||
| 86.17 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 78.51 | 0.22 | /workspace/coverage/default/39.chip_sw_all_escalation_resets.2288758345 | ||
| 86.20 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 78.73 | 0.22 | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2133690885 | ||
| 86.24 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 78.95 | 0.22 | /workspace/coverage/default/40.chip_sw_all_escalation_resets.3234490835 | ||
| 86.28 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 79.17 | 0.22 | /workspace/coverage/default/42.chip_sw_all_escalation_resets.2001897383 | ||
| 86.31 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 79.39 | 0.22 | /workspace/coverage/default/43.chip_sw_all_escalation_resets.2869671602 | ||
| 86.35 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 79.61 | 0.22 | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2342313681 | ||
| 86.38 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 79.82 | 0.22 | /workspace/coverage/default/45.chip_sw_all_escalation_resets.2539043414 | ||
| 86.42 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 80.04 | 0.22 | /workspace/coverage/default/46.chip_sw_all_escalation_resets.2840194875 | ||
| 86.46 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 80.26 | 0.22 | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3916798337 | ||
| 86.49 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 80.48 | 0.22 | /workspace/coverage/default/48.chip_sw_all_escalation_resets.1372091156 | ||
| 86.53 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 80.70 | 0.22 | /workspace/coverage/default/49.chip_sw_all_escalation_resets.2874439214 | ||
| 86.57 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 80.92 | 0.22 | /workspace/coverage/default/5.chip_sw_all_escalation_resets.1117047350 | ||
| 86.60 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 81.14 | 0.22 | /workspace/coverage/default/50.chip_sw_all_escalation_resets.1606643441 | ||
| 86.64 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 81.36 | 0.22 | /workspace/coverage/default/54.chip_sw_all_escalation_resets.1113777691 | ||
| 86.68 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 81.58 | 0.22 | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1034147970 | ||
| 86.71 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 81.80 | 0.22 | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2264504799 | ||
| 86.75 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 82.02 | 0.22 | /workspace/coverage/default/63.chip_sw_all_escalation_resets.3707279400 | ||
| 86.79 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 82.24 | 0.22 | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2807055709 | ||
| 86.82 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 82.46 | 0.22 | /workspace/coverage/default/64.chip_sw_all_escalation_resets.3695087716 | ||
| 86.86 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 82.68 | 0.22 | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2702200374 | ||
| 86.90 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 82.89 | 0.22 | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.207484528 | ||
| 86.93 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 83.11 | 0.22 | /workspace/coverage/default/75.chip_sw_all_escalation_resets.1877299219 | ||
| 86.97 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 83.33 | 0.22 | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3774793491 | ||
| 87.01 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 83.55 | 0.22 | /workspace/coverage/default/87.chip_sw_all_escalation_resets.1656861599 | ||
| 87.04 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 83.77 | 0.22 | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2429589735 | ||
| 87.08 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.11 | 0.00 | 91.15 | 0.00 | 96.33 | 0.00 | 83.99 | 0.22 | /workspace/coverage/default/91.chip_sw_all_escalation_resets.1800260969 | ||
| 87.11 | 0.04 | 88.67 | 0.00 | 78.23 | 0.00 | 84.15 | 0.04 | 91.15 | 0.00 | 96.50 | 0.17 | 83.99 | 0.00 | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3745591945 | ||
| 87.15 | 0.03 | 88.67 | 0.01 | 78.31 | 0.09 | 84.16 | 0.01 | 91.24 | 0.10 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3061694704 | ||
| 87.18 | 0.03 | 88.68 | 0.01 | 78.32 | 0.01 | 84.34 | 0.18 | 91.24 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3452100691 | ||
| 87.21 | 0.03 | 88.68 | 0.00 | 78.32 | 0.00 | 84.52 | 0.18 | 91.24 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.586612747 | ||
| 87.24 | 0.03 | 88.80 | 0.12 | 78.35 | 0.03 | 84.52 | 0.01 | 91.28 | 0.03 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1442554199 | ||
| 87.27 | 0.03 | 88.85 | 0.06 | 78.39 | 0.05 | 84.53 | 0.01 | 91.33 | 0.06 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_plic_sw_irq.335491830 | ||
| 87.29 | 0.02 | 88.85 | 0.00 | 78.39 | 0.00 | 84.67 | 0.14 | 91.33 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1069581998 | ||
| 87.31 | 0.02 | 88.91 | 0.06 | 78.46 | 0.06 | 84.67 | 0.00 | 91.35 | 0.02 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.2284842736 | ||
| 87.33 | 0.02 | 88.91 | 0.00 | 78.58 | 0.12 | 84.67 | 0.00 | 91.35 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_plic_all_irqs_0.3690687085 | ||
| 87.35 | 0.02 | 88.94 | 0.03 | 78.64 | 0.06 | 84.67 | 0.01 | 91.37 | 0.02 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.736899876 | ||
| 87.37 | 0.02 | 88.94 | 0.00 | 78.64 | 0.00 | 84.78 | 0.11 | 91.37 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2450296722 | ||
| 87.39 | 0.02 | 88.94 | 0.00 | 78.64 | 0.00 | 84.89 | 0.11 | 91.37 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3417343292 | ||
| 87.40 | 0.02 | 88.94 | 0.00 | 78.64 | 0.00 | 84.98 | 0.09 | 91.37 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2663491462 | ||
| 87.42 | 0.01 | 88.94 | 0.00 | 78.72 | 0.08 | 84.98 | 0.00 | 91.37 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_plic_all_irqs_20.3051106079 | ||
| 87.43 | 0.01 | 88.97 | 0.03 | 78.75 | 0.04 | 84.98 | 0.00 | 91.38 | 0.01 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.1939430372 | ||
| 87.44 | 0.01 | 89.04 | 0.07 | 78.76 | 0.01 | 84.98 | 0.00 | 91.38 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3142259425 | ||
| 87.46 | 0.01 | 89.06 | 0.02 | 78.78 | 0.02 | 84.99 | 0.01 | 91.41 | 0.02 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/22.chip_sw_all_escalation_resets.1275728858 | ||
| 87.47 | 0.01 | 89.07 | 0.01 | 78.82 | 0.04 | 84.99 | 0.00 | 91.43 | 0.02 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2661143055 | ||
| 87.48 | 0.01 | 89.07 | 0.00 | 78.82 | 0.00 | 85.06 | 0.07 | 91.43 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/1.chip_sw_flash_init.613679023 | ||
| 87.49 | 0.01 | 89.10 | 0.02 | 78.83 | 0.02 | 85.08 | 0.03 | 91.43 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/2.chip_sw_power_sleep_load.4093595146 | ||
| 87.50 | 0.01 | 89.10 | 0.01 | 78.84 | 0.01 | 85.12 | 0.04 | 91.44 | 0.01 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.390609489 | ||
| 87.51 | 0.01 | 89.13 | 0.02 | 78.85 | 0.01 | 85.13 | 0.01 | 91.46 | 0.02 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2264012960 | ||
| 87.52 | 0.01 | 89.13 | 0.00 | 78.89 | 0.04 | 85.13 | 0.00 | 91.46 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/2.chip_plic_all_irqs_0.128568220 | ||
| 87.52 | 0.01 | 89.13 | 0.00 | 78.93 | 0.04 | 85.13 | 0.00 | 91.46 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/1.chip_plic_all_irqs_10.971900514 | ||
| 87.53 | 0.01 | 89.16 | 0.03 | 78.93 | 0.01 | 85.13 | 0.00 | 91.46 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_spi_device_tpm.895277801 | ||
| 87.54 | 0.01 | 89.16 | 0.00 | 78.93 | 0.00 | 85.17 | 0.04 | 91.46 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_jtag_mem_access.1825445363 | ||
| 87.54 | 0.01 | 89.16 | 0.00 | 78.93 | 0.00 | 85.20 | 0.04 | 91.46 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_kmac_app_rom.413172937 | ||
| 87.55 | 0.01 | 89.16 | 0.00 | 78.93 | 0.00 | 85.24 | 0.03 | 91.46 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3567251210 | ||
| 87.55 | 0.01 | 89.16 | 0.00 | 78.93 | 0.00 | 85.27 | 0.03 | 91.46 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.862958076 | ||
| 87.56 | 0.01 | 89.18 | 0.01 | 78.93 | 0.00 | 85.29 | 0.02 | 91.46 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/2.chip_sw_pattgen_ios.1381058667 | ||
| 87.56 | 0.01 | 89.18 | 0.00 | 78.94 | 0.01 | 85.31 | 0.03 | 91.46 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.124707259 | ||
| 87.57 | 0.01 | 89.18 | 0.00 | 78.95 | 0.01 | 85.31 | 0.00 | 91.47 | 0.02 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1594190800 | ||
| 87.57 | 0.01 | 89.18 | 0.00 | 78.98 | 0.03 | 85.31 | 0.00 | 91.47 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/2.chip_plic_all_irqs_20.3372192714 | ||
| 87.58 | 0.01 | 89.18 | 0.00 | 79.00 | 0.02 | 85.31 | 0.00 | 91.47 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2574335075 | ||
| 87.58 | 0.01 | 89.18 | 0.00 | 79.02 | 0.01 | 85.32 | 0.01 | 91.47 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2122486830 | ||
| 87.58 | 0.01 | 89.18 | 0.00 | 79.02 | 0.00 | 85.35 | 0.02 | 91.47 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.4217262820 | ||
| 87.59 | 0.01 | 89.18 | 0.01 | 79.03 | 0.01 | 85.35 | 0.01 | 91.47 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3695294292 | ||
| 87.59 | 0.01 | 89.18 | 0.00 | 79.03 | 0.00 | 85.37 | 0.01 | 91.48 | 0.01 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.132169879 | ||
| 87.60 | 0.01 | 89.18 | 0.00 | 79.03 | 0.00 | 85.39 | 0.02 | 91.48 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/1.chip_sw_aon_timer_irq.2565780015 | ||
| 87.60 | 0.01 | 89.19 | 0.01 | 79.04 | 0.01 | 85.39 | 0.01 | 91.48 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1514835322 | ||
| 87.60 | 0.01 | 89.19 | 0.01 | 79.04 | 0.01 | 85.39 | 0.01 | 91.48 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1805797818 | ||
| 87.60 | 0.01 | 89.20 | 0.01 | 79.04 | 0.01 | 85.40 | 0.01 | 91.48 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.296354869 | ||
| 87.61 | 0.01 | 89.20 | 0.00 | 79.06 | 0.01 | 85.40 | 0.00 | 91.48 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_plic_all_irqs_10.4049108637 | ||
| 87.61 | 0.01 | 89.20 | 0.00 | 79.07 | 0.01 | 85.40 | 0.00 | 91.48 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.625969525 | ||
| 87.61 | 0.01 | 89.20 | 0.00 | 79.08 | 0.01 | 85.40 | 0.00 | 91.48 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_uart_tx_rx.1530361309 | ||
| 87.61 | 0.01 | 89.20 | 0.00 | 79.08 | 0.00 | 85.41 | 0.01 | 91.48 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_edn_boot_mode.2349089349 | ||
| 87.61 | 0.01 | 89.20 | 0.00 | 79.09 | 0.01 | 85.42 | 0.01 | 91.48 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.372252048 | ||
| 87.62 | 0.01 | 89.20 | 0.00 | 79.09 | 0.00 | 85.43 | 0.01 | 91.48 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.422032611 | ||
| 87.62 | 0.01 | 89.21 | 0.01 | 79.09 | 0.00 | 85.44 | 0.01 | 91.48 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2660331366 | ||
| 87.62 | 0.01 | 89.21 | 0.00 | 79.10 | 0.01 | 85.44 | 0.00 | 91.48 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.907635241 | ||
| 87.62 | 0.01 | 89.21 | 0.00 | 79.11 | 0.01 | 85.44 | 0.00 | 91.48 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.64954347 | ||
| 87.62 | 0.01 | 89.21 | 0.01 | 79.11 | 0.00 | 85.45 | 0.01 | 91.48 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1767405481 | ||
| 87.63 | 0.01 | 89.21 | 0.01 | 79.11 | 0.00 | 85.45 | 0.01 | 91.48 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/3.chip_tap_straps_testunlock0.1017970967 | ||
| 87.63 | 0.01 | 89.21 | 0.00 | 79.11 | 0.00 | 85.46 | 0.01 | 91.48 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1896384779 | ||
| 87.63 | 0.01 | 89.21 | 0.00 | 79.11 | 0.00 | 85.46 | 0.00 | 91.49 | 0.01 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/1.chip_tap_straps_dev.2936430241 | ||
| 87.63 | 0.01 | 89.21 | 0.00 | 79.12 | 0.01 | 85.46 | 0.00 | 91.49 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.387227861 | ||
| 87.63 | 0.01 | 89.21 | 0.00 | 79.12 | 0.00 | 85.47 | 0.01 | 91.49 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_flash_init.711338866 | ||
| 87.63 | 0.01 | 89.21 | 0.00 | 79.12 | 0.00 | 85.47 | 0.01 | 91.49 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_kmac_idle.2701389895 | ||
| 87.63 | 0.01 | 89.21 | 0.00 | 79.12 | 0.00 | 85.48 | 0.01 | 91.49 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3080460486 | ||
| 87.63 | 0.01 | 89.21 | 0.00 | 79.12 | 0.00 | 85.48 | 0.01 | 91.49 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.4223576298 | ||
| 87.63 | 0.01 | 89.21 | 0.00 | 79.12 | 0.00 | 85.49 | 0.01 | 91.49 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/1.chip_sw_power_sleep_load.2026169932 | ||
| 87.63 | 0.01 | 89.21 | 0.00 | 79.12 | 0.01 | 85.49 | 0.00 | 91.49 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1770105262 | ||
| 87.63 | 0.01 | 89.21 | 0.00 | 79.12 | 0.00 | 85.49 | 0.01 | 91.49 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3122465302 | ||
| 87.63 | 0.01 | 89.21 | 0.00 | 79.12 | 0.00 | 85.49 | 0.01 | 91.49 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2884003204 | ||
| 87.64 | 0.01 | 89.21 | 0.00 | 79.12 | 0.00 | 85.49 | 0.01 | 91.49 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3392148831 | ||
| 87.64 | 0.01 | 89.21 | 0.00 | 79.12 | 0.00 | 85.50 | 0.01 | 91.49 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2910198578 | ||
| 87.64 | 0.01 | 89.21 | 0.00 | 79.12 | 0.00 | 85.50 | 0.01 | 91.49 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2921420640 | ||
| 87.64 | 0.01 | 89.21 | 0.00 | 79.12 | 0.00 | 85.50 | 0.01 | 91.49 | 0.00 | 96.50 | 0.00 | 83.99 | 0.00 | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.279591292 | ||
| Name |
|---|
| /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.533243357 |
| /workspace/coverage/default/0.chip_sival_flash_info_access.4046393865 |
| /workspace/coverage/default/0.chip_sw_aes_enc.3960041474 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.186255838 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2817999310 |
| /workspace/coverage/default/0.chip_sw_aes_entropy.317537292 |
| /workspace/coverage/default/0.chip_sw_aes_idle.2129991747 |
| /workspace/coverage/default/0.chip_sw_aes_masking_off.4141053370 |
| /workspace/coverage/default/0.chip_sw_aes_smoketest.504164879 |
| /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2146354918 |
| /workspace/coverage/default/0.chip_sw_alert_handler_escalation.931508430 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2173640958 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.4262109079 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2610202572 |
| /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.803121452 |
| /workspace/coverage/default/0.chip_sw_alert_test.2844050555 |
| /workspace/coverage/default/0.chip_sw_aon_timer_irq.3544801271 |
| /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2062793874 |
| /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.182511048 |
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| /workspace/coverage/default/88.chip_sw_all_escalation_resets.3594802575 |
| /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4072733609 |
| /workspace/coverage/default/9.chip_sw_all_escalation_resets.1647634955 |
| /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1826288952 |
| /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.551658441 |
| /workspace/coverage/default/90.chip_sw_all_escalation_resets.614833835 |
| /workspace/coverage/default/93.chip_sw_all_escalation_resets.730995835 |
| /workspace/coverage/default/94.chip_sw_all_escalation_resets.2752367879 |
| /workspace/coverage/default/95.chip_sw_all_escalation_resets.3144123137 |
| /workspace/coverage/default/96.chip_sw_all_escalation_resets.2244825571 |
| /workspace/coverage/default/97.chip_sw_all_escalation_resets.3070005209 |
| /workspace/coverage/default/98.chip_sw_all_escalation_resets.2639145340 |
| /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3224197007 |
| /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3070048873 |
| /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3177611444 |
| /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2232407829 |
| /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3090371666 |
| /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.393352615 |
| /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3310347967 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T4 | /workspace/coverage/default/12.chip_sw_all_escalation_resets.2640567666 | May 28 04:19:28 PM PDT 24 | May 28 04:28:41 PM PDT 24 | 5681070816 ps | ||
| T5 | /workspace/coverage/default/2.chip_sw_aon_timer_irq.3614724170 | May 28 04:07:19 PM PDT 24 | May 28 04:14:05 PM PDT 24 | 3800289720 ps | ||
| T6 | /workspace/coverage/default/24.chip_sw_all_escalation_resets.1336540031 | May 28 04:21:27 PM PDT 24 | May 28 04:30:48 PM PDT 24 | 4904769740 ps | ||
| T67 | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.198383560 | May 28 04:26:58 PM PDT 24 | May 28 04:34:48 PM PDT 24 | 3433595948 ps | ||
| T68 | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2817999310 | May 28 03:49:01 PM PDT 24 | May 28 03:52:41 PM PDT 24 | 3044396598 ps | ||
| T18 | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3567251210 | May 28 03:47:04 PM PDT 24 | May 28 03:58:12 PM PDT 24 | 6521936696 ps | ||
| T69 | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.240829074 | May 28 04:02:37 PM PDT 24 | May 28 04:42:37 PM PDT 24 | 27141950116 ps | ||
| T19 | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2247943627 | May 28 03:55:15 PM PDT 24 | May 28 03:59:29 PM PDT 24 | 3171913980 ps | ||
| T72 | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.907635241 | May 28 03:49:06 PM PDT 24 | May 28 03:56:29 PM PDT 24 | 6063301672 ps | ||
| T62 | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1483387664 | May 28 04:03:36 PM PDT 24 | May 28 04:15:50 PM PDT 24 | 4386814488 ps | ||
| T48 | /workspace/coverage/default/61.chip_sw_all_escalation_resets.3470888143 | May 28 04:26:33 PM PDT 24 | May 28 04:37:14 PM PDT 24 | 4751742518 ps | ||
| T61 | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3241802195 | May 28 04:11:07 PM PDT 24 | May 28 04:49:53 PM PDT 24 | 12046450120 ps | ||
| T217 | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1038650482 | May 28 04:25:51 PM PDT 24 | May 28 04:33:47 PM PDT 24 | 3432897132 ps | ||
| T21 | /workspace/coverage/default/1.chip_jtag_mem_access.3376441960 | May 28 03:54:03 PM PDT 24 | May 28 04:23:57 PM PDT 24 | 13404836246 ps | ||
| T265 | /workspace/coverage/default/0.chip_sw_pattgen_ios.16180533 | May 28 03:41:48 PM PDT 24 | May 28 03:45:41 PM PDT 24 | 2721508056 ps | ||
| T273 | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1765846919 | May 28 04:29:18 PM PDT 24 | May 28 04:35:43 PM PDT 24 | 4135360264 ps | ||
| T215 | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1408660044 | May 28 04:25:23 PM PDT 24 | May 28 04:33:02 PM PDT 24 | 3914162230 ps | ||
| T308 | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.273244767 | May 28 03:54:07 PM PDT 24 | May 28 04:00:54 PM PDT 24 | 3455561868 ps | ||
| T241 | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.397284115 | May 28 04:00:04 PM PDT 24 | May 28 04:07:52 PM PDT 24 | 2904422975 ps | ||
| T203 | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.270275507 | May 28 03:56:07 PM PDT 24 | May 28 04:06:41 PM PDT 24 | 3646322768 ps | ||
| T20 | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.99953214 | May 28 04:20:09 PM PDT 24 | May 28 05:11:59 PM PDT 24 | 14224463304 ps | ||
| T266 | /workspace/coverage/default/2.chip_sw_pattgen_ios.1381058667 | May 28 04:04:12 PM PDT 24 | May 28 04:08:57 PM PDT 24 | 2743543642 ps | ||
| T89 | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3971921135 | May 28 03:48:47 PM PDT 24 | May 28 03:53:15 PM PDT 24 | 2425260028 ps | ||
| T26 | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1235697939 | May 28 03:55:18 PM PDT 24 | May 28 04:52:25 PM PDT 24 | 14690345308 ps | ||
| T223 | /workspace/coverage/default/2.chip_sw_example_rom.3776555014 | May 28 04:04:12 PM PDT 24 | May 28 04:06:13 PM PDT 24 | 2462153376 ps | ||
| T136 | /workspace/coverage/default/0.chip_sw_edn_boot_mode.2349089349 | May 28 03:47:18 PM PDT 24 | May 28 03:56:50 PM PDT 24 | 3060028652 ps | ||
| T242 | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1283395629 | May 28 03:43:23 PM PDT 24 | May 28 03:56:21 PM PDT 24 | 5228970146 ps | ||
| T214 | /workspace/coverage/default/1.chip_sw_flash_crash_alert.743392744 | May 28 04:02:48 PM PDT 24 | May 28 04:12:36 PM PDT 24 | 5082017126 ps | ||
| T81 | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.387227861 | May 28 03:44:42 PM PDT 24 | May 28 04:10:13 PM PDT 24 | 10902065588 ps | ||
| T139 | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3435184982 | May 28 04:09:08 PM PDT 24 | May 28 04:24:21 PM PDT 24 | 5710320552 ps | ||
| T90 | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3176080191 | May 28 04:03:06 PM PDT 24 | May 28 04:07:26 PM PDT 24 | 2834107342 ps | ||
| T58 | /workspace/coverage/default/1.chip_tap_straps_dev.2936430241 | May 28 04:01:48 PM PDT 24 | May 28 04:11:02 PM PDT 24 | 6145120732 ps | ||
| T262 | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3444037695 | May 28 04:19:21 PM PDT 24 | May 28 04:29:58 PM PDT 24 | 4146739720 ps | ||
| T22 | /workspace/coverage/default/0.chip_jtag_mem_access.1825445363 | May 28 03:40:56 PM PDT 24 | May 28 04:05:57 PM PDT 24 | 12985453545 ps | ||
| T179 | /workspace/coverage/default/25.chip_sw_all_escalation_resets.439488077 | May 28 04:21:05 PM PDT 24 | May 28 04:31:42 PM PDT 24 | 5856717072 ps | ||
| T128 | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1212926203 | May 28 04:14:48 PM PDT 24 | May 28 05:14:59 PM PDT 24 | 16334250591 ps | ||
| T196 | /workspace/coverage/default/1.chip_sw_aes_enc.105270608 | May 28 03:59:20 PM PDT 24 | May 28 04:03:58 PM PDT 24 | 2730120440 ps | ||
| T154 | /workspace/coverage/default/1.chip_sw_power_idle_load.1772308694 | May 28 04:03:01 PM PDT 24 | May 28 04:17:02 PM PDT 24 | 4115245892 ps | ||
| T348 | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2621887231 | May 28 04:09:09 PM PDT 24 | May 28 04:16:09 PM PDT 24 | 3912830840 ps | ||
| T129 | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2661143055 | May 28 03:44:28 PM PDT 24 | May 28 03:55:06 PM PDT 24 | 4317053290 ps | ||
| T323 | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.4061175659 | May 28 04:12:48 PM PDT 24 | May 28 04:19:59 PM PDT 24 | 3608274284 ps | ||
| T32 | /workspace/coverage/default/89.chip_sw_all_escalation_resets.650271702 | May 28 04:27:37 PM PDT 24 | May 28 04:34:32 PM PDT 24 | 5579846920 ps | ||
| T153 | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.228265464 | May 28 04:17:26 PM PDT 24 | May 28 04:31:16 PM PDT 24 | 5128289392 ps | ||
| T506 | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2658087019 | May 28 03:46:28 PM PDT 24 | May 28 03:50:18 PM PDT 24 | 3083331234 ps | ||
| T325 | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.105689426 | May 28 04:26:55 PM PDT 24 | May 28 04:34:12 PM PDT 24 | 3707551104 ps | ||
| T197 | /workspace/coverage/default/1.chip_sw_aes_masking_off.3527644175 | May 28 03:58:31 PM PDT 24 | May 28 04:03:18 PM PDT 24 | 3353312218 ps | ||
| T372 | /workspace/coverage/default/42.chip_sw_all_escalation_resets.2001897383 | May 28 04:23:51 PM PDT 24 | May 28 04:33:27 PM PDT 24 | 4144946600 ps | ||
| T326 | /workspace/coverage/default/31.chip_sw_all_escalation_resets.1383436473 | May 28 04:22:31 PM PDT 24 | May 28 04:31:30 PM PDT 24 | 4901959390 ps | ||
| T507 | /workspace/coverage/default/2.chip_sw_example_manufacturer.2679350773 | May 28 04:04:31 PM PDT 24 | May 28 04:08:17 PM PDT 24 | 2356232136 ps | ||
| T330 | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2264504799 | May 28 04:25:45 PM PDT 24 | May 28 04:32:52 PM PDT 24 | 3639097860 ps | ||
| T472 | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.176425881 | May 28 04:22:48 PM PDT 24 | May 28 04:28:35 PM PDT 24 | 4113278988 ps | ||
| T191 | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.296354869 | May 28 03:59:25 PM PDT 24 | May 28 04:03:49 PM PDT 24 | 2726768882 ps | ||
| T33 | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1232772205 | May 28 03:47:05 PM PDT 24 | May 28 03:54:44 PM PDT 24 | 9904522517 ps | ||
| T53 | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3016891399 | May 28 04:19:58 PM PDT 24 | May 28 05:00:02 PM PDT 24 | 11278945119 ps | ||
| T86 | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3110299104 | May 28 03:53:41 PM PDT 24 | May 28 04:07:41 PM PDT 24 | 6927345656 ps | ||
| T104 | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2558018787 | May 28 03:45:19 PM PDT 24 | May 28 04:12:03 PM PDT 24 | 23447396350 ps | ||
| T54 | /workspace/coverage/default/2.rom_e2e_shutdown_output.3547862333 | May 28 04:21:59 PM PDT 24 | May 28 05:03:47 PM PDT 24 | 23856807859 ps | ||
| T134 | /workspace/coverage/default/2.chip_sw_power_sleep_load.4093595146 | May 28 04:16:03 PM PDT 24 | May 28 04:22:17 PM PDT 24 | 4811893232 ps | ||
| T176 | /workspace/coverage/default/2.chip_sw_kmac_app_rom.22820950 | May 28 04:11:36 PM PDT 24 | May 28 04:16:52 PM PDT 24 | 2790447880 ps | ||
| T177 | /workspace/coverage/default/0.chip_sw_kmac_app_rom.413172937 | May 28 03:48:56 PM PDT 24 | May 28 03:53:13 PM PDT 24 | 2684386670 ps | ||
| T508 | /workspace/coverage/default/2.chip_sw_aes_entropy.2294984378 | May 28 04:09:52 PM PDT 24 | May 28 04:13:03 PM PDT 24 | 2261553404 ps | ||
| T95 | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.1423838720 | May 28 04:08:12 PM PDT 24 | May 28 04:19:52 PM PDT 24 | 6089266225 ps | ||
| T159 | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3069635854 | May 28 04:24:55 PM PDT 24 | May 28 04:32:07 PM PDT 24 | 3669801360 ps | ||
| T165 | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.848143991 | May 28 03:43:06 PM PDT 24 | May 28 04:05:19 PM PDT 24 | 8687831404 ps | ||
| T166 | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2807055709 | May 28 04:26:06 PM PDT 24 | May 28 04:31:35 PM PDT 24 | 2854289374 ps | ||
| T167 | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.625840887 | May 28 04:08:15 PM PDT 24 | May 28 04:11:28 PM PDT 24 | 2303324472 ps | ||
| T98 | /workspace/coverage/default/1.chip_sw_gpio.183193704 | May 28 03:55:17 PM PDT 24 | May 28 04:04:47 PM PDT 24 | 3922156914 ps | ||
| T168 | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.4182417147 | May 28 03:48:07 PM PDT 24 | May 28 03:55:49 PM PDT 24 | 5323731800 ps | ||
| T137 | /workspace/coverage/default/0.chip_sw_edn_auto_mode.2034711130 | May 28 03:47:03 PM PDT 24 | May 28 04:15:09 PM PDT 24 | 6026765230 ps | ||
| T83 | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1272821942 | May 28 04:27:26 PM PDT 24 | May 28 04:34:30 PM PDT 24 | 4082205114 ps | ||
| T63 | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2302952483 | May 28 04:08:34 PM PDT 24 | May 28 05:10:25 PM PDT 24 | 14262657310 ps | ||
| T169 | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.397209059 | May 28 04:22:24 PM PDT 24 | May 28 05:19:45 PM PDT 24 | 14833837488 ps | ||
| T509 | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.633709237 | May 28 03:58:01 PM PDT 24 | May 28 04:12:36 PM PDT 24 | 5503469928 ps | ||
| T510 | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1858291222 | May 28 04:17:30 PM PDT 24 | May 28 04:25:41 PM PDT 24 | 6658803548 ps | ||
| T122 | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1304080860 | May 28 03:55:49 PM PDT 24 | May 28 05:26:10 PM PDT 24 | 22537192852 ps | ||
| T37 | /workspace/coverage/default/2.chip_tap_straps_prod.411458622 | May 28 04:12:29 PM PDT 24 | May 28 04:15:04 PM PDT 24 | 2211862037 ps | ||
| T66 | /workspace/coverage/default/0.rom_e2e_smoke.4115356730 | May 28 03:55:00 PM PDT 24 | May 28 05:02:13 PM PDT 24 | 13743510256 ps | ||
| T274 | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3819266958 | May 28 03:55:48 PM PDT 24 | May 28 04:03:23 PM PDT 24 | 6215611790 ps | ||
| T213 | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3629641247 | May 28 04:01:52 PM PDT 24 | May 28 04:21:00 PM PDT 24 | 7223152747 ps | ||
| T290 | /workspace/coverage/default/36.chip_sw_all_escalation_resets.3714133140 | May 28 04:22:13 PM PDT 24 | May 28 04:37:41 PM PDT 24 | 6042694644 ps | ||
| T193 | /workspace/coverage/default/2.chip_sw_kmac_idle.1116372553 | May 28 04:11:37 PM PDT 24 | May 28 04:15:02 PM PDT 24 | 2469738736 ps | ||
| T123 | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.519627249 | May 28 04:17:43 PM PDT 24 | May 28 04:58:53 PM PDT 24 | 13508718855 ps | ||
| T59 | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.596795864 | May 28 04:06:53 PM PDT 24 | May 28 04:32:25 PM PDT 24 | 9101812172 ps | ||
| T291 | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.635845156 | May 28 03:57:36 PM PDT 24 | May 28 04:59:14 PM PDT 24 | 14755659856 ps | ||
| T138 | /workspace/coverage/default/2.chip_sw_edn_auto_mode.1122249463 | May 28 04:09:40 PM PDT 24 | May 28 04:40:27 PM PDT 24 | 6932562982 ps | ||
| T82 | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1387809535 | May 28 03:56:20 PM PDT 24 | May 28 04:27:49 PM PDT 24 | 9539970360 ps | ||
| T257 | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1930364767 | May 28 04:24:20 PM PDT 24 | May 28 04:30:05 PM PDT 24 | 4451586872 ps | ||
| T1 | /workspace/coverage/default/0.chip_jtag_csr_rw.2479444655 | May 28 03:41:04 PM PDT 24 | May 28 04:03:27 PM PDT 24 | 12113910608 ps | ||
| T375 | /workspace/coverage/default/2.chip_sw_csrng_smoketest.1514214481 | May 28 04:16:43 PM PDT 24 | May 28 04:20:38 PM PDT 24 | 3019170936 ps | ||
| T135 | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.124707259 | May 28 03:53:47 PM PDT 24 | May 28 04:02:24 PM PDT 24 | 17609821258 ps | ||
| T324 | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2176722614 | May 28 04:08:30 PM PDT 24 | May 28 04:29:40 PM PDT 24 | 12162006401 ps | ||
| T41 | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3417343292 | May 28 03:48:49 PM PDT 24 | May 28 03:58:34 PM PDT 24 | 4650792440 ps | ||
| T43 | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2146354918 | May 28 03:46:45 PM PDT 24 | May 28 03:52:32 PM PDT 24 | 3791655234 ps | ||
| T376 | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1213686341 | May 28 04:07:37 PM PDT 24 | May 28 04:17:09 PM PDT 24 | 4253458680 ps | ||
| T374 | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2704494722 | May 28 03:47:48 PM PDT 24 | May 28 03:58:57 PM PDT 24 | 5738496664 ps | ||
| T2 | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2283167094 | May 28 04:00:58 PM PDT 24 | May 28 04:08:27 PM PDT 24 | 7671053800 ps | ||
| T172 | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3761667942 | May 28 04:03:07 PM PDT 24 | May 28 04:07:28 PM PDT 24 | 3673366963 ps | ||
| T173 | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.1447453894 | May 28 04:06:54 PM PDT 24 | May 28 04:16:27 PM PDT 24 | 4520289960 ps | ||
| T55 | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2545923545 | May 28 03:55:04 PM PDT 24 | May 28 04:44:39 PM PDT 24 | 10646295848 ps | ||
| T156 | /workspace/coverage/default/2.chip_tap_straps_rma.2984272825 | May 28 04:12:56 PM PDT 24 | May 28 04:17:50 PM PDT 24 | 4484853617 ps | ||
| T60 | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3898101727 | May 28 03:55:07 PM PDT 24 | May 28 04:16:11 PM PDT 24 | 9063098084 ps | ||
| T99 | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2510863496 | May 28 04:21:19 PM PDT 24 | May 28 04:46:13 PM PDT 24 | 9289268580 ps | ||
| T100 | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.918016648 | May 28 04:05:40 PM PDT 24 | May 28 04:17:52 PM PDT 24 | 4086935620 ps | ||
| T30 | /workspace/coverage/default/1.chip_sw_alert_test.3588610024 | May 28 03:59:39 PM PDT 24 | May 28 04:04:52 PM PDT 24 | 2874781568 ps | ||
| T174 | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2174457059 | May 28 03:56:54 PM PDT 24 | May 28 04:55:54 PM PDT 24 | 14260763512 ps | ||
| T56 | /workspace/coverage/default/1.rom_e2e_shutdown_output.3368505559 | May 28 04:08:59 PM PDT 24 | May 28 04:56:23 PM PDT 24 | 22572166923 ps | ||
| T42 | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3856085622 | May 28 04:13:09 PM PDT 24 | May 28 04:25:27 PM PDT 24 | 4869581310 ps | ||
| T194 | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3670104338 | May 28 03:46:55 PM PDT 24 | May 28 03:51:48 PM PDT 24 | 2907715579 ps | ||
| T511 | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3620393477 | May 28 03:43:50 PM PDT 24 | May 28 03:54:05 PM PDT 24 | 4893656824 ps | ||
| T512 | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.4128280396 | May 28 04:13:39 PM PDT 24 | May 28 04:18:11 PM PDT 24 | 2733715746 ps | ||
| T426 | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.414599620 | May 28 03:51:23 PM PDT 24 | May 28 04:08:26 PM PDT 24 | 5466484178 ps | ||
| T192 | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.811046559 | May 28 04:13:27 PM PDT 24 | May 28 04:17:18 PM PDT 24 | 3519536612 ps | ||
| T513 | /workspace/coverage/default/2.chip_sw_csrng_kat_test.3456581797 | May 28 04:12:35 PM PDT 24 | May 28 04:16:51 PM PDT 24 | 2978038760 ps | ||
| T264 | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1249043482 | May 28 03:54:46 PM PDT 24 | May 28 04:05:59 PM PDT 24 | 4070486178 ps | ||
| T91 | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1677643165 | May 28 04:14:20 PM PDT 24 | May 28 04:20:09 PM PDT 24 | 3381099500 ps | ||
| T221 | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.4028345075 | May 28 04:11:29 PM PDT 24 | May 28 04:55:59 PM PDT 24 | 12956099340 ps | ||
| T514 | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.338409633 | May 28 03:59:46 PM PDT 24 | May 28 04:02:52 PM PDT 24 | 3232190658 ps | ||
| T263 | /workspace/coverage/default/2.chip_sw_plic_sw_irq.1985601414 | May 28 04:13:03 PM PDT 24 | May 28 04:18:26 PM PDT 24 | 2186097040 ps | ||
| T280 | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.725955656 | May 28 03:56:54 PM PDT 24 | May 28 05:19:46 PM PDT 24 | 17464298480 ps | ||
| T124 | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.1516564309 | May 28 04:05:19 PM PDT 24 | May 28 07:02:14 PM PDT 24 | 64664203981 ps | ||
| T349 | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.995566784 | May 28 03:56:08 PM PDT 24 | May 28 04:14:26 PM PDT 24 | 7413276163 ps | ||
| T3 | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2959723631 | May 28 03:42:21 PM PDT 24 | May 28 03:45:54 PM PDT 24 | 2762819454 ps | ||
| T49 | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3375267290 | May 28 04:09:40 PM PDT 24 | May 28 04:27:53 PM PDT 24 | 4714197960 ps | ||
| T38 | /workspace/coverage/default/1.chip_tap_straps_rma.446906879 | May 28 04:02:11 PM PDT 24 | May 28 04:04:08 PM PDT 24 | 2430969368 ps | ||
| T321 | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3221351568 | May 28 04:20:58 PM PDT 24 | May 28 04:47:02 PM PDT 24 | 8104881916 ps | ||
| T75 | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2164696781 | May 28 04:03:17 PM PDT 24 | May 28 05:04:15 PM PDT 24 | 24311474494 ps | ||
| T267 | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1442554199 | May 28 03:53:13 PM PDT 24 | May 28 03:58:05 PM PDT 24 | 2696187390 ps | ||
| T175 | /workspace/coverage/default/21.chip_sw_all_escalation_resets.3912042637 | May 28 04:21:33 PM PDT 24 | May 28 04:30:01 PM PDT 24 | 4770842600 ps | ||
| T96 | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3452100691 | May 28 03:43:36 PM PDT 24 | May 28 03:52:00 PM PDT 24 | 3874160769 ps | ||
| T125 | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.511730360 | May 28 03:44:41 PM PDT 24 | May 28 03:51:54 PM PDT 24 | 8601306310 ps | ||
| T87 | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1958650677 | May 28 03:46:36 PM PDT 24 | May 28 03:55:08 PM PDT 24 | 3838899464 ps | ||
| T198 | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.4257867603 | May 28 04:01:08 PM PDT 24 | May 28 04:06:53 PM PDT 24 | 4720922930 ps | ||
| T500 | /workspace/coverage/default/17.chip_sw_all_escalation_resets.3470434539 | May 28 04:23:35 PM PDT 24 | May 28 04:33:02 PM PDT 24 | 4640458340 ps | ||
| T64 | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1517865429 | May 28 04:18:54 PM PDT 24 | May 28 05:07:23 PM PDT 24 | 13740818068 ps | ||
| T105 | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.623178428 | May 28 03:57:55 PM PDT 24 | May 28 04:24:03 PM PDT 24 | 21473215770 ps | ||
| T222 | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3136599389 | May 28 04:17:14 PM PDT 24 | May 28 05:08:05 PM PDT 24 | 12351548342 ps | ||
| T414 | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4072733609 | May 28 04:18:31 PM PDT 24 | May 28 04:25:38 PM PDT 24 | 3822481180 ps | ||
| T76 | /workspace/coverage/default/0.chip_sw_otbn_smoketest.2970359563 | May 28 03:53:41 PM PDT 24 | May 28 04:19:05 PM PDT 24 | 6576433000 ps | ||
| T130 | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.586612747 | May 28 04:02:16 PM PDT 24 | May 28 04:20:26 PM PDT 24 | 6245750599 ps | ||
| T226 | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2660331366 | May 28 03:42:37 PM PDT 24 | May 28 03:55:10 PM PDT 24 | 4567871650 ps | ||
| T224 | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1918157624 | May 28 04:13:07 PM PDT 24 | May 28 04:38:12 PM PDT 24 | 6824766760 ps | ||
| T424 | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.4093524719 | May 28 03:48:48 PM PDT 24 | May 28 04:05:50 PM PDT 24 | 7071299356 ps | ||
| T423 | /workspace/coverage/default/40.chip_sw_all_escalation_resets.3234490835 | May 28 04:22:32 PM PDT 24 | May 28 04:33:04 PM PDT 24 | 5453093440 ps | ||
| T515 | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.186255838 | May 28 03:45:57 PM PDT 24 | May 28 03:49:25 PM PDT 24 | 2377100520 ps | ||
| T132 | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2308793999 | May 28 03:42:20 PM PDT 24 | May 28 03:51:47 PM PDT 24 | 4505093971 ps | ||
| T268 | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.271867765 | May 28 03:57:09 PM PDT 24 | May 28 04:01:33 PM PDT 24 | 2920534440 ps | ||
| T239 | /workspace/coverage/default/1.chip_tap_straps_prod.3745208765 | May 28 04:02:52 PM PDT 24 | May 28 04:35:19 PM PDT 24 | 16976265084 ps | ||
| T516 | /workspace/coverage/default/0.rom_e2e_asm_init_prod.1552545727 | May 28 03:55:07 PM PDT 24 | May 28 05:05:23 PM PDT 24 | 13717973061 ps | ||
| T227 | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2194069907 | May 28 04:06:35 PM PDT 24 | May 28 04:24:23 PM PDT 24 | 4947074440 ps | ||
| T195 | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1170544640 | May 28 04:15:12 PM PDT 24 | May 28 04:20:28 PM PDT 24 | 3083267614 ps | ||
| T401 | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.106760942 | May 28 04:26:44 PM PDT 24 | May 28 04:32:44 PM PDT 24 | 3764108800 ps | ||
| T277 | /workspace/coverage/default/59.chip_sw_all_escalation_resets.2390755865 | May 28 04:29:18 PM PDT 24 | May 28 04:37:18 PM PDT 24 | 5115810700 ps | ||
| T46 | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2750498459 | May 28 03:58:57 PM PDT 24 | May 28 07:45:01 PM PDT 24 | 255069493058 ps | ||
| T84 | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2566849712 | May 28 04:29:50 PM PDT 24 | May 28 04:35:21 PM PDT 24 | 3483567564 ps | ||
| T312 | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2280866978 | May 28 03:56:14 PM PDT 24 | May 28 04:43:05 PM PDT 24 | 10279939848 ps | ||
| T313 | /workspace/coverage/default/39.chip_sw_all_escalation_resets.2288758345 | May 28 04:24:16 PM PDT 24 | May 28 04:35:02 PM PDT 24 | 6272911664 ps | ||
| T314 | /workspace/coverage/default/2.chip_sw_hmac_enc.1767657803 | May 28 04:10:59 PM PDT 24 | May 28 04:14:46 PM PDT 24 | 2613338764 ps | ||
| T315 | /workspace/coverage/default/1.chip_sw_kmac_smoketest.3832225973 | May 28 04:05:12 PM PDT 24 | May 28 04:11:35 PM PDT 24 | 2658559164 ps | ||
| T73 | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1251110972 | May 28 04:11:04 PM PDT 24 | May 28 04:28:39 PM PDT 24 | 9591762238 ps | ||
| T316 | /workspace/coverage/default/15.chip_sw_all_escalation_resets.568381532 | May 28 04:20:07 PM PDT 24 | May 28 04:30:50 PM PDT 24 | 4538383820 ps | ||
| T317 | /workspace/coverage/default/9.chip_sw_all_escalation_resets.1647634955 | May 28 04:20:08 PM PDT 24 | May 28 04:27:57 PM PDT 24 | 5458883000 ps | ||
| T216 | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3250882684 | May 28 04:00:02 PM PDT 24 | May 28 04:09:32 PM PDT 24 | 5259928004 ps | ||
| T65 | /workspace/coverage/default/2.chip_sw_flash_init.1756194540 | May 28 04:04:49 PM PDT 24 | May 28 04:36:19 PM PDT 24 | 19670979616 ps | ||
| T517 | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2210060494 | May 28 03:43:29 PM PDT 24 | May 28 04:01:23 PM PDT 24 | 6159498889 ps | ||
| T420 | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2406754891 | May 28 04:26:00 PM PDT 24 | May 28 04:33:10 PM PDT 24 | 4180409224 ps | ||
| T518 | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4252070847 | May 28 04:00:40 PM PDT 24 | May 28 04:23:45 PM PDT 24 | 7942856629 ps | ||
| T519 | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1677759712 | May 28 04:14:06 PM PDT 24 | May 28 04:31:52 PM PDT 24 | 7124573131 ps | ||
| T520 | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2034380003 | May 28 03:57:57 PM PDT 24 | May 28 04:58:21 PM PDT 24 | 13879811828 ps | ||
| T521 | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3819654300 | May 28 04:17:30 PM PDT 24 | May 28 04:30:00 PM PDT 24 | 3876678130 ps | ||
| T92 | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3061694704 | May 28 03:42:10 PM PDT 24 | May 28 03:48:02 PM PDT 24 | 2786955006 ps | ||
| T187 | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.345673093 | May 28 03:56:18 PM PDT 24 | May 28 04:03:47 PM PDT 24 | 4303402884 ps | ||
| T425 | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.370213612 | May 28 04:21:02 PM PDT 24 | May 28 04:29:05 PM PDT 24 | 3989801832 ps | ||
| T93 | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2479178414 | May 28 04:04:27 PM PDT 24 | May 28 04:11:20 PM PDT 24 | 2745993083 ps | ||
| T483 | /workspace/coverage/default/37.chip_sw_all_escalation_resets.2274733087 | May 28 04:22:17 PM PDT 24 | May 28 04:31:35 PM PDT 24 | 6383927310 ps | ||
| T522 | /workspace/coverage/default/0.rom_keymgr_functest.2124070107 | May 28 03:54:14 PM PDT 24 | May 28 04:04:08 PM PDT 24 | 4479735830 ps | ||
| T109 | /workspace/coverage/default/1.chip_sw_gpio_smoketest.2706089721 | May 28 04:05:07 PM PDT 24 | May 28 04:10:15 PM PDT 24 | 3017199121 ps | ||
| T523 | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3691917301 | May 28 04:03:34 PM PDT 24 | May 28 04:08:12 PM PDT 24 | 3339183944 ps | ||
| T524 | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.900443922 | May 28 04:07:57 PM PDT 24 | May 28 05:03:35 PM PDT 24 | 14862643994 ps | ||
| T141 | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.683936471 | May 28 04:17:35 PM PDT 24 | May 28 04:30:41 PM PDT 24 | 5570905952 ps | ||
| T116 | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3142259425 | May 28 03:45:32 PM PDT 24 | May 28 03:52:27 PM PDT 24 | 6185821352 ps | ||
| T188 | /workspace/coverage/default/1.chip_plic_all_irqs_20.1589354567 | May 28 04:03:27 PM PDT 24 | May 28 04:18:03 PM PDT 24 | 4205789300 ps | ||
| T283 | /workspace/coverage/default/2.chip_sw_rv_timer_irq.2134275237 | May 28 04:06:42 PM PDT 24 | May 28 04:09:40 PM PDT 24 | 2493784152 ps | ||
| T525 | /workspace/coverage/default/2.chip_sw_uart_smoketest.3276227977 | May 28 04:17:12 PM PDT 24 | May 28 04:23:45 PM PDT 24 | 2676630328 ps | ||
| T427 | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1654474728 | May 28 04:25:22 PM PDT 24 | May 28 04:31:44 PM PDT 24 | 3222912740 ps | ||
| T34 | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3742536803 | May 28 04:03:16 PM PDT 24 | May 28 04:12:38 PM PDT 24 | 4592841080 ps | ||
| T97 | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3713067788 | May 28 03:58:43 PM PDT 24 | May 28 04:05:37 PM PDT 24 | 3984907394 ps | ||
| T101 | /workspace/coverage/default/0.chip_sw_usbdev_vbus.719292353 | May 28 03:42:08 PM PDT 24 | May 28 03:45:36 PM PDT 24 | 2778570226 ps | ||
| T344 | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3254820660 | May 28 04:17:16 PM PDT 24 | May 28 04:27:46 PM PDT 24 | 3845338608 ps | ||
| T249 | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.480892629 | May 28 03:54:08 PM PDT 24 | May 28 04:05:10 PM PDT 24 | 5229618137 ps | ||
| T526 | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.182511048 | May 28 03:52:45 PM PDT 24 | May 28 03:57:20 PM PDT 24 | 3166255738 ps | ||
| T357 | /workspace/coverage/default/29.chip_sw_all_escalation_resets.1144700054 | May 28 04:21:54 PM PDT 24 | May 28 04:33:01 PM PDT 24 | 5626687064 ps | ||
| T259 | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1112301215 | May 28 04:26:52 PM PDT 24 | May 28 04:32:33 PM PDT 24 | 2920930340 ps | ||
| T339 | /workspace/coverage/default/2.chip_sw_otbn_randomness.1805103999 | May 28 04:12:22 PM PDT 24 | May 28 04:27:50 PM PDT 24 | 6158925024 ps | ||
| T340 | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3176418781 | May 28 04:27:04 PM PDT 24 | May 28 04:33:52 PM PDT 24 | 4268521672 ps | ||
| T341 | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2341838309 | May 28 03:44:15 PM PDT 24 | May 28 04:36:19 PM PDT 24 | 29096735232 ps | ||
| T181 | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.4011686317 | May 28 04:12:19 PM PDT 24 | May 28 04:36:04 PM PDT 24 | 13040953656 ps | ||
| T77 | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.4135928402 | May 28 03:57:30 PM PDT 24 | May 28 05:01:31 PM PDT 24 | 18584852077 ps | ||
| T160 | /workspace/coverage/default/0.chip_sw_gpio_smoketest.1940125390 | May 28 03:52:50 PM PDT 24 | May 28 03:57:56 PM PDT 24 | 2785953547 ps | ||
| T342 | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3062284576 | May 28 04:06:27 PM PDT 24 | May 28 04:11:57 PM PDT 24 | 3603524846 ps | ||
| T228 | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.741750805 | May 28 03:44:45 PM PDT 24 | May 28 03:56:04 PM PDT 24 | 4016883636 ps | ||
| T343 | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.885228789 | May 28 04:16:05 PM PDT 24 | May 28 04:22:04 PM PDT 24 | 5748586944 ps | ||
| T371 | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3392148831 | May 28 03:45:10 PM PDT 24 | May 28 04:14:34 PM PDT 24 | 12725962852 ps | ||
| T50 | /workspace/coverage/default/35.chip_sw_all_escalation_resets.2701757325 | May 28 04:24:15 PM PDT 24 | May 28 04:33:50 PM PDT 24 | 4990336004 ps | ||
| T88 | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.126292058 | May 28 04:00:51 PM PDT 24 | May 28 04:08:24 PM PDT 24 | 3975473754 ps | ||
| T331 | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.124227544 | May 28 04:00:50 PM PDT 24 | May 28 04:41:50 PM PDT 24 | 10409699004 ps | ||
| T74 | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1461775768 | May 28 04:09:52 PM PDT 24 | May 28 04:21:28 PM PDT 24 | 4618591450 ps | ||
| T527 | /workspace/coverage/default/1.chip_sw_example_manufacturer.2620727407 | May 28 03:53:30 PM PDT 24 | May 28 03:57:13 PM PDT 24 | 2743702960 ps | ||
| T528 | /workspace/coverage/default/2.chip_sw_aes_smoketest.3181469838 | May 28 04:16:32 PM PDT 24 | May 28 04:21:37 PM PDT 24 | 2929252940 ps | ||
| T219 | /workspace/coverage/default/0.chip_plic_all_irqs_20.3051106079 | May 28 04:00:58 PM PDT 24 | May 28 04:13:30 PM PDT 24 | 4473279772 ps | ||
| T529 | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2650564612 | May 28 04:19:01 PM PDT 24 | May 28 05:19:32 PM PDT 24 | 16357362960 ps | ||
| T345 | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3584839488 | May 28 04:04:34 PM PDT 24 | May 28 04:13:57 PM PDT 24 | 3495758548 ps | ||
| T530 | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3095765756 | May 28 04:18:48 PM PDT 24 | May 28 04:24:03 PM PDT 24 | 3037304028 ps | ||
| T457 | /workspace/coverage/default/97.chip_sw_all_escalation_resets.3070005209 | May 28 04:28:53 PM PDT 24 | May 28 04:38:49 PM PDT 24 | 6171456556 ps | ||
| T190 | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1171535063 | May 28 03:44:10 PM PDT 24 | May 28 03:50:17 PM PDT 24 | 4854915666 ps | ||
| T531 | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1196895490 | May 28 04:16:47 PM PDT 24 | May 28 04:20:04 PM PDT 24 | 2790371312 ps | ||
| T532 | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1639066864 | May 28 04:03:13 PM PDT 24 | May 28 04:14:19 PM PDT 24 | 7341366510 ps | ||
| T182 | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2195410311 | May 28 04:00:40 PM PDT 24 | May 28 04:19:29 PM PDT 24 | 8286540404 ps | ||
| T484 | /workspace/coverage/default/96.chip_sw_all_escalation_resets.2244825571 | May 28 04:30:13 PM PDT 24 | May 28 04:39:25 PM PDT 24 | 3963531722 ps | ||
| T71 | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.422032611 | May 28 03:43:58 PM PDT 24 | May 28 04:07:31 PM PDT 24 | 6562158862 ps | ||
| T502 | /workspace/coverage/default/86.chip_sw_all_escalation_resets.2667131753 | May 28 04:29:59 PM PDT 24 | May 28 04:39:51 PM PDT 24 | 4833332280 ps | ||
| T278 | /workspace/coverage/default/44.chip_sw_all_escalation_resets.4021779248 | May 28 04:23:45 PM PDT 24 | May 28 04:33:17 PM PDT 24 | 5082919320 ps | ||
| T355 | /workspace/coverage/default/2.chip_sw_uart_tx_rx.2017102484 | May 28 04:05:48 PM PDT 24 | May 28 04:17:19 PM PDT 24 | 4676244840 ps | ||
| T533 | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.4267935743 | May 28 04:17:05 PM PDT 24 | May 28 04:34:36 PM PDT 24 | 7047979640 ps | ||
| T31 | /workspace/coverage/default/0.chip_sw_alert_test.2844050555 | May 28 03:46:53 PM PDT 24 | May 28 03:51:27 PM PDT 24 | 3377759000 ps | ||
| T534 | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1865248605 | May 28 04:17:06 PM PDT 24 | May 28 04:25:22 PM PDT 24 | 4001188827 ps | ||
| T535 | /workspace/coverage/default/0.chip_sw_otbn_randomness.374075128 | May 28 03:45:33 PM PDT 24 | May 28 04:02:00 PM PDT 24 | 6042644476 ps | ||
| T57 | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.4285971913 | May 28 03:55:36 PM PDT 24 | May 28 04:40:59 PM PDT 24 | 10542987628 ps | ||
| T275 | /workspace/coverage/default/18.chip_sw_all_escalation_resets.1109056640 | May 28 04:20:12 PM PDT 24 | May 28 04:29:26 PM PDT 24 | 5231121150 ps | ||
| T447 | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3932265236 | May 28 04:23:43 PM PDT 24 | May 28 04:30:30 PM PDT 24 | 4141795126 ps | ||
| T131 | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2372430282 | May 28 04:14:12 PM PDT 24 | May 28 04:23:48 PM PDT 24 | 5660359668 ps | ||
| T303 | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.374068379 | May 28 03:46:55 PM PDT 24 | May 28 03:55:42 PM PDT 24 | 4683371286 ps | ||
| T536 | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2295976048 | May 28 03:43:46 PM PDT 24 | May 28 04:11:57 PM PDT 24 | 8197262880 ps | ||
| T428 | /workspace/coverage/default/63.chip_sw_all_escalation_resets.3707279400 | May 28 04:25:56 PM PDT 24 | May 28 04:34:58 PM PDT 24 | 4289621868 ps | ||
| T537 | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2179288355 | May 28 03:57:46 PM PDT 24 | May 28 04:07:22 PM PDT 24 | 4395931760 ps | ||
| T27 | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3808703662 | May 28 04:11:11 PM PDT 24 | May 28 04:22:07 PM PDT 24 | 6045812796 ps | ||
| T538 | /workspace/coverage/default/1.rom_e2e_asm_init_prod.192549403 | May 28 04:07:42 PM PDT 24 | May 28 05:18:31 PM PDT 24 | 15280661368 ps | ||
| T142 | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.352663898 | May 28 03:47:33 PM PDT 24 | May 28 03:55:33 PM PDT 24 | 4590749208 ps | ||
| T539 | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.596727247 | May 28 04:19:33 PM PDT 24 | May 28 04:39:28 PM PDT 24 | 7319467814 ps | ||
| T258 | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2975930794 | May 28 04:25:19 PM PDT 24 | May 28 04:33:26 PM PDT 24 | 3136709184 ps | ||
| T260 | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3172711098 | May 28 04:27:28 PM PDT 24 | May 28 04:32:41 PM PDT 24 | 4374726748 ps | ||
| T47 | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1922755327 | May 28 04:10:51 PM PDT 24 | May 28 07:41:04 PM PDT 24 | 255467064796 ps | ||
| T335 | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.118470188 | May 28 03:51:06 PM PDT 24 | May 28 04:08:55 PM PDT 24 | 7477211341 ps | ||
| T360 | /workspace/coverage/default/27.chip_sw_all_escalation_resets.1477112709 | May 28 04:22:31 PM PDT 24 | May 28 04:30:35 PM PDT 24 | 5417038780 ps | ||
| T540 | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3346869126 | May 28 03:55:42 PM PDT 24 | May 28 03:59:24 PM PDT 24 | 3375085888 ps | ||
| T442 | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3192070728 | May 28 04:26:39 PM PDT 24 | May 28 04:33:07 PM PDT 24 | 3962394492 ps | ||
| T358 | /workspace/coverage/default/1.chip_sw_all_escalation_resets.2731351883 | May 28 03:54:16 PM PDT 24 | May 28 04:06:13 PM PDT 24 | 5200734088 ps | ||
| T270 | /workspace/coverage/default/1.chip_sw_plic_sw_irq.1611718909 | May 28 04:00:50 PM PDT 24 | May 28 04:05:54 PM PDT 24 | 2514643574 ps | ||
| T541 | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.335610627 | May 28 03:52:30 PM PDT 24 | May 28 03:56:49 PM PDT 24 | 2862937768 ps | ||
| T542 | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2881136733 | May 28 03:57:58 PM PDT 24 | May 28 04:12:48 PM PDT 24 | 5181862752 ps | ||
| T279 | /workspace/coverage/default/60.chip_sw_all_escalation_resets.1319631848 | May 28 04:26:20 PM PDT 24 | May 28 04:38:23 PM PDT 24 | 5761301620 ps |
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