Unified Coverage Report :: Module :: tlul_cmd_intg_gen

Module : tlul_cmd_intg_gen

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_cmd_intg_gen	87.50	75.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_cmd_intg_gen	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_cmd_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	75.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12	88.24					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.26	90.91	69.23			88.89	100.00	tl_adapter_host_i_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cmd_gen	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_cmd_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.91	91.30	82.35			90.00	100.00	tl_adapter_host_d_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cmd_gen	100.00	100.00

Line Coverage for Module : tlul_cmd_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
ALWAYS	46	4	4	100.00
CONT_ASSIGN	54	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	1	1
41	1	1
42	1	1
46	1	1
47	1	1
48	1	1
49	1	1
54	1	1

---

Assert Coverage for Module : tlul_cmd_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayMaxWidthCheck_A	1846	1846	0	0

PayMaxWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1846	1846	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T62	2	2	0	0
T67	2	2	0	0
T68	2	2	0	0
T69	2	2	0	0
T72	2	2	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_cmd_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		8	6	75.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	42	1	0	0.00
ALWAYS	46	4	4	100.00
CONT_ASSIGN	54	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	1	1
41	0	1
42	0	1
46	1	1
47	1	1
48	1	1
49	1	1
54	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_cmd_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayMaxWidthCheck_A	923	923	0	0

PayMaxWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_cmd_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
ALWAYS	46	4	4	100.00
CONT_ASSIGN	54	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	1	1
41	1	1
42	1	1
46	1	1
47	1	1
48	1	1
49	1	1
54	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_cmd_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayMaxWidthCheck_A	923	923	0	0

PayMaxWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0