Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395372364	45586120	0	0
DepthKnown_A	395372364	395281777	0	0
RvalidKnown_A	395372364	395281777	0	0
WreadyKnown_A	395372364	395281777	0	0
gen_passthru_fifo.paramCheckPass	923	923	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	45586120	0	0
T4	261933	33944	0	0
T5	167368	11732	0	0
T6	234648	28752	0	0
T18	302611	35380	0	0
T19	97772	10428	0	0
T62	231580	28108	0	0
T67	166514	26908	0	0
T68	72021	7937	0	0
T69	916519	108026	0	0
T72	157469	18887	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395372364	37043844	0	0
DepthKnown_A	395372364	395281777	0	0
RvalidKnown_A	395372364	395281777	0	0
WreadyKnown_A	395372364	395281777	0	0
gen_passthru_fifo.paramCheckPass	923	923	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	37043844	0	0
T4	261933	24258	0	0
T5	167368	8331	0	0
T6	234648	19945	0	0
T18	302611	25509	0	0
T19	97772	8316	0	0
T62	231580	22106	0	0
T67	166514	19280	0	0
T68	72021	5503	0	0
T69	916519	75630	0	0
T72	157469	13592	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395372364	37255606	0	0
DepthKnown_A	395372364	395281777	0	0
RvalidKnown_A	395372364	395281777	0	0
WreadyKnown_A	395372364	395281777	0	0
gen_passthru_fifo.paramCheckPass	923	923	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	37255606	0	0
T4	261933	17739	0	0
T5	167368	4161	0	0
T6	234648	15131	0	0
T18	302611	18263	0	0
T19	97772	5296	0	0
T62	231580	17092	0	0
T67	166514	9986	0	0
T68	72021	3494	0	0
T69	916519	63232	0	0
T72	157469	9478	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395372364	31801821	0	0
DepthKnown_A	395372364	395281777	0	0
RvalidKnown_A	395372364	395281777	0	0
WreadyKnown_A	395372364	395281777	0	0
gen_passthru_fifo.paramCheckPass	923	923	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	31801821	0	0
T4	261933	17356	0	0
T5	167368	3993	0	0
T6	234648	14768	0	0
T18	302611	17704	0	0
T19	97772	5165	0	0
T62	231580	16711	0	0
T67	166514	9712	0	0
T68	72021	3351	0	0
T69	916519	61578	0	0
T72	157469	9171	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395372364	61845	0	0
DepthKnown_A	395372364	395281777	0	0
RvalidKnown_A	395372364	395281777	0	0
WreadyKnown_A	395372364	395281777	0	0
gen_passthru_fifo.paramCheckPass	923	923	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	61845	0	0
T4	261933	151	0	0
T5	167368	25	0	0
T6	234648	153	0	0
T18	302611	72	0	0
T19	97772	13	0	0
T62	231580	104	0	0
T67	166514	26	0	0
T68	72021	13	0	0
T69	916519	209	0	0
T72	157469	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395372364	61845	0	0
DepthKnown_A	395372364	395281777	0	0
RvalidKnown_A	395372364	395281777	0	0
WreadyKnown_A	395372364	395281777	0	0
gen_passthru_fifo.paramCheckPass	923	923	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	61845	0	0
T4	261933	151	0	0
T5	167368	25	0	0
T6	234648	153	0	0
T18	302611	72	0	0
T19	97772	13	0	0
T62	231580	104	0	0
T67	166514	26	0	0
T68	72021	13	0	0
T69	916519	209	0	0
T72	157469	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395372364	48364	0	0
DepthKnown_A	395372364	395281777	0	0
RvalidKnown_A	395372364	395281777	0	0
WreadyKnown_A	395372364	395281777	0	0
gen_passthru_fifo.paramCheckPass	923	923	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	48364	0	0
T4	261933	95	0	0
T5	167368	22	0	0
T6	234648	97	0	0
T18	302611	68	0	0
T19	97772	12	0	0
T62	231580	98	0	0
T67	166514	23	0	0
T68	72021	12	0	0
T69	916519	198	0	0
T72	157469	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395372364	48364	0	0
DepthKnown_A	395372364	395281777	0	0
RvalidKnown_A	395372364	395281777	0	0
WreadyKnown_A	395372364	395281777	0	0
gen_passthru_fifo.paramCheckPass	923	923	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	48364	0	0
T4	261933	95	0	0
T5	167368	22	0	0
T6	234648	97	0	0
T18	302611	68	0	0
T19	97772	12	0	0
T62	231580	98	0	0
T67	166514	23	0	0
T68	72021	12	0	0
T69	916519	198	0	0
T72	157469	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395372364	13481	0	0
DepthKnown_A	395372364	395281777	0	0
RvalidKnown_A	395372364	395281777	0	0
WreadyKnown_A	395372364	395281777	0	0
gen_passthru_fifo.paramCheckPass	923	923	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	13481	0	0
T4	261933	56	0	0
T5	167368	3	0	0
T6	234648	56	0	0
T18	302611	4	0	0
T19	97772	1	0	0
T62	231580	6	0	0
T67	166514	3	0	0
T68	72021	1	0	0
T69	916519	11	0	0
T72	157469	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395372364	13481	0	0
DepthKnown_A	395372364	395281777	0	0
RvalidKnown_A	395372364	395281777	0	0
WreadyKnown_A	395372364	395281777	0	0
gen_passthru_fifo.paramCheckPass	923	923	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	13481	0	0
T4	261933	56	0	0
T5	167368	3	0	0
T6	234648	56	0	0
T18	302611	4	0	0
T19	97772	1	0	0
T62	231580	6	0	0
T67	166514	3	0	0
T68	72021	1	0	0
T69	916519	11	0	0
T72	157469	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	395281777	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0