Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.88 90.18 60.26 97.06 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 86.88 90.18 60.26 97.06 100.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL1528137890.18
ALWAYS6844100.00
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CONT_ASSIGN1622711100.00
CONT_ASSIGN1624111100.00
CONT_ASSIGN1627511100.00
CONT_ASSIGN1628911100.00
ALWAYS16295199199100.00
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CONT_ASSIGN1731911100.00
CONT_ASSIGN1732111100.00
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CONT_ASSIGN1732711100.00
CONT_ASSIGN1732911100.00
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ALWAYS17634199199100.00
ALWAYS1783755240272.83
CONT_ASSIGN1899400
CONT_ASSIGN1900211100.00
CONT_ASSIGN1900311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
16227 1 1
16241 1 1
16275 1 1
16289 1 1
16295 1 1
16296 1 1
16297 1 1
16298 1 1
16299 1 1
16300 1 1
16301 1 1
16302 1 1
16303 1 1
16304 1 1
16305 1 1
16306 1 1
16307 1 1
16308 1 1
16309 1 1
16310 1 1
16311 1 1
16312 1 1
16313 1 1
16314 1 1
16315 1 1
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16318 1 1
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16327 1 1
16328 1 1
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16330 1 1
16331 1 1
16332 1 1
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16335 1 1
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18964 1 1
18968 1 1
18972 1 1
18976 1 1
18980 1 1
18994 unreachable
19002 1 1
19003 1 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions1983119560.26
Logical1983119560.26
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-1648597.21
16486-1650044.54
16500-1693056.89
16933-1762851.94

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 204 198 97.06
TERNARY 16496 2 2 100.00
IF 68 3 3 100.00
CASE 17838 199 193 96.98

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16496 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T259,T260,T261
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 17838 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T4,T5,T6
addr_hit[1] Covered T262,T123,T263
addr_hit[2] Covered T262,T123,T263
addr_hit[3] Covered T262,T123,T263
addr_hit[4] Covered T262,T123,T263
addr_hit[5] Covered T262,T123,T263
addr_hit[6] Covered T262,T123,T263
addr_hit[7] Covered T262,T123,T263
addr_hit[8] Covered T262,T123,T263
addr_hit[9] Covered T264,T263,T132
addr_hit[10] Covered T264,T263,T132
addr_hit[11] Covered T264,T263,T132
addr_hit[12] Covered T264,T263,T132
addr_hit[13] Covered T264,T263,T132
addr_hit[14] Covered T264,T263,T132
addr_hit[15] Covered T264,T263,T132
addr_hit[16] Covered T264,T263,T132
addr_hit[17] Covered T153,T263,T188
addr_hit[18] Covered T153,T263,T188
addr_hit[19] Covered T153,T263,T188
addr_hit[20] Covered T153,T263,T188
addr_hit[21] Covered T153,T263,T188
addr_hit[22] Covered T153,T263,T188
addr_hit[23] Covered T153,T263,T188
addr_hit[24] Covered T153,T263,T188
addr_hit[25] Covered T99,T100,T263
addr_hit[26] Covered T99,T100,T263
addr_hit[27] Covered T99,T100,T263
addr_hit[28] Covered T99,T100,T263
addr_hit[29] Covered T99,T100,T263
addr_hit[30] Covered T99,T100,T263
addr_hit[31] Covered T99,T100,T263
addr_hit[32] Covered T99,T100,T263
addr_hit[33] Covered T98,T263,T188
addr_hit[34] Covered T98,T263,T188
addr_hit[35] Covered T98,T263,T188
addr_hit[36] Covered T98,T263,T188
addr_hit[37] Covered T98,T263,T188
addr_hit[38] Covered T98,T263,T188
addr_hit[39] Covered T98,T263,T188
addr_hit[40] Covered T98,T263,T188
addr_hit[41] Covered T98,T263,T188
addr_hit[42] Covered T98,T263,T188
addr_hit[43] Covered T98,T263,T188
addr_hit[44] Covered T98,T263,T188
addr_hit[45] Covered T98,T263,T188
addr_hit[46] Covered T98,T263,T188
addr_hit[47] Covered T98,T263,T188
addr_hit[48] Covered T98,T263,T188
addr_hit[49] Covered T98,T263,T188
addr_hit[50] Covered T98,T263,T188
addr_hit[51] Covered T98,T263,T188
addr_hit[52] Covered T98,T263,T188
addr_hit[53] Covered T98,T263,T188
addr_hit[54] Covered T98,T263,T188
addr_hit[55] Covered T98,T263,T188
addr_hit[56] Covered T98,T263,T188
addr_hit[57] Covered T98,T263,T188
addr_hit[58] Covered T98,T263,T188
addr_hit[59] Covered T98,T263,T188
addr_hit[60] Covered T98,T263,T188
addr_hit[61] Covered T98,T263,T188
addr_hit[62] Covered T98,T263,T188
addr_hit[63] Covered T98,T263,T188
addr_hit[64] Covered T98,T263,T188
addr_hit[65] Covered T95,T98,T263
addr_hit[66] Covered T263,T188,T219
addr_hit[67] Covered T263,T188,T219
addr_hit[68] Covered T95,T263,T96
addr_hit[69] Covered T95,T263,T96
addr_hit[70] Covered T263,T188,T219
addr_hit[71] Covered T263,T188,T219
addr_hit[72] Covered T263,T188,T219
addr_hit[73] Covered T263,T188,T219
addr_hit[74] Covered T263,T188,T219
addr_hit[75] Covered T263,T188,T219
addr_hit[76] Covered T263,T188,T219
addr_hit[77] Covered T263,T188,T219
addr_hit[78] Covered T263,T188,T219
addr_hit[79] Covered T263,T188,T219
addr_hit[80] Covered T263,T188,T219
addr_hit[81] Covered T263,T188,T219
addr_hit[82] Covered T263,T188,T219
addr_hit[83] Covered T263,T188,T219
addr_hit[84] Covered T263,T188,T219
addr_hit[85] Covered T263,T188,T219
addr_hit[86] Covered T263,T188,T219
addr_hit[87] Covered T263,T188,T219
addr_hit[88] Covered T263,T226,T227
addr_hit[89] Covered T263,T226,T227
addr_hit[90] Covered T263,T188,T219
addr_hit[91] Covered T263,T226,T227
addr_hit[92] Covered T263,T226,T227
addr_hit[93] Covered T263,T226,T227
addr_hit[94] Covered T263,T226,T227
addr_hit[95] Covered T263,T226,T227
addr_hit[96] Covered T263,T188,T219
addr_hit[97] Covered T263,T226,T227
addr_hit[98] Covered T263,T188,T228
addr_hit[99] Covered T263,T188,T219
addr_hit[100] Covered T263,T188,T228
addr_hit[101] Covered T263,T188,T228
addr_hit[102] Covered T263,T188,T228
addr_hit[103] Covered T263,T188,T219
addr_hit[104] Covered T263,T188,T219
addr_hit[105] Covered T263,T188,T219
addr_hit[106] Covered T263,T188,T219
addr_hit[107] Covered T263,T188,T219
addr_hit[108] Covered T263,T188,T219
addr_hit[109] Covered T263,T188,T219
addr_hit[110] Covered T263,T188,T219
addr_hit[111] Covered T263,T188,T219
addr_hit[112] Covered T263,T188,T219
addr_hit[113] Covered T263,T188,T219
addr_hit[114] Covered T263,T188,T219
addr_hit[115] Covered T263,T188,T219
addr_hit[116] Covered T263,T188,T219
addr_hit[117] Covered T263,T188,T219
addr_hit[118] Covered T265,T266,T263
addr_hit[119] Covered T265,T266,T263
addr_hit[120] Covered T263,T188,T219
addr_hit[121] Covered T263,T188,T219
addr_hit[122] Covered T263,T188,T219
addr_hit[123] Covered T4,T6,T48
addr_hit[124] Covered T4,T6,T48
addr_hit[125] Covered T4,T6,T48
addr_hit[126] Covered T4,T6,T48
addr_hit[127] Covered T95,T263,T96
addr_hit[128] Covered T95,T263,T96
addr_hit[129] Covered T263,T188,T219
addr_hit[130] Covered T263,T188,T219
addr_hit[131] Covered T263,T188,T219
addr_hit[132] Covered T263,T188,T219
addr_hit[133] Covered T263,T188,T219
addr_hit[134] Covered T263,T188,T219
addr_hit[135] Covered T263,T188,T219
addr_hit[136] Covered T263,T188,T219
addr_hit[137] Covered T263,T188,T219
addr_hit[138] Covered T263,T188,T219
addr_hit[139] Covered T263,T188,T219
addr_hit[140] Covered T263,T188,T219
addr_hit[141] Covered T263,T188,T219
addr_hit[142] Covered T263,T188,T219
addr_hit[143] Covered T263,T188,T219
addr_hit[144] Covered T263,T188,T219
addr_hit[145] Covered T263,T188,T219
addr_hit[146] Covered T263,T188,T219
addr_hit[147] Covered T263,T188,T219
addr_hit[148] Covered T263,T188,T219
addr_hit[149] Covered T67,T72,T217
addr_hit[150] Covered T263,T188,T249
addr_hit[151] Covered T135,T263,T188
addr_hit[152] Covered T4,T5,T6
addr_hit[153] Covered T4,T5,T6
addr_hit[154] Covered T263,T188,T219
addr_hit[155] Covered T263,T188,T219
addr_hit[156] Covered T203,T129,T263
addr_hit[157] Covered T203,T129,T263
addr_hit[158] Covered T203,T129,T263
addr_hit[159] Covered T203,T129,T263
addr_hit[160] Covered T203,T129,T263
addr_hit[161] Covered T263,T188,T219
addr_hit[162] Covered T191,T172,T192
addr_hit[163] Covered T191,T172,T192
addr_hit[164] Covered T263,T188,T219
addr_hit[165] Covered T263,T188,T219
addr_hit[166] Covered T263,T188,T219
addr_hit[167] Covered T263,T188,T219
addr_hit[168] Covered T263,T75,T188
addr_hit[169] Covered T263,T188,T219
addr_hit[170] Covered T263,T188,T219
addr_hit[171] Covered T263,T188,T219
addr_hit[172] Covered T263,T188,T219
addr_hit[173] Covered T263,T188,T219
addr_hit[174] Covered T263,T188,T219
addr_hit[175] Covered T263,T188,T219
addr_hit[176] Covered T263,T188,T219
addr_hit[177] Covered T263,T188,T219
addr_hit[178] Covered T263,T188,T219
addr_hit[179] Covered T263,T188,T219
addr_hit[180] Covered T263,T188,T219
addr_hit[181] Covered T263,T188,T219
addr_hit[182] Not Covered
addr_hit[183] Not Covered
addr_hit[184] Not Covered
addr_hit[185] Not Covered
addr_hit[186] Covered T267,T268,T269
addr_hit[187] Not Covered
addr_hit[188] Covered T262,T153,T123
addr_hit[189] Covered T98,T99,T100
addr_hit[190] Covered T95,T98,T263
addr_hit[191] Covered T4,T6,T48
addr_hit[192] Covered T4,T5,T6
addr_hit[193] Covered T203,T129,T191
addr_hit[194] Covered T4,T5,T6
addr_hit[195] Covered T4,T5,T6
addr_hit[196] Covered T134,T263,T270
addr_hit[197] Covered T30,T31,T155
default Not Covered


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 395372364 34111 0 0
reAfterRv 395372364 34111 0 0
rePulse 395372364 13896 0 0
wePulse 395372364 20215 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 395372364 34111 0 0
T4 261933 44 0 0
T5 167368 11 0 0
T6 234648 44 0 0
T18 302611 0 0 0
T19 97772 0 0 0
T48 0 44 0 0
T62 231580 0 0 0
T67 166514 8 0 0
T68 72021 0 0 0
T69 916519 0 0 0
T72 157469 10 0 0
T215 0 8 0 0
T217 0 8 0 0
T265 0 9 0 0
T273 0 8 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 395372364 34111 0 0
T4 261933 44 0 0
T5 167368 11 0 0
T6 234648 44 0 0
T18 302611 0 0 0
T19 97772 0 0 0
T48 0 44 0 0
T62 231580 0 0 0
T67 166514 8 0 0
T68 72021 0 0 0
T69 916519 0 0 0
T72 157469 10 0 0
T215 0 8 0 0
T217 0 8 0 0
T265 0 9 0 0
T273 0 8 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 395372364 13896 0 0
T4 261933 14 0 0
T5 167368 4 0 0
T6 234648 14 0 0
T18 302611 0 0 0
T19 97772 0 0 0
T48 0 14 0 0
T62 231580 0 0 0
T67 166514 3 0 0
T68 72021 0 0 0
T69 916519 0 0 0
T72 157469 3 0 0
T215 0 3 0 0
T217 0 3 0 0
T265 0 4 0 0
T273 0 3 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 395372364 20215 0 0
T4 261933 30 0 0
T5 167368 7 0 0
T6 234648 30 0 0
T18 302611 0 0 0
T19 97772 0 0 0
T48 0 30 0 0
T62 231580 0 0 0
T67 166514 5 0 0
T68 72021 0 0 0
T69 916519 0 0 0
T72 157469 7 0 0
T215 0 5 0 0
T217 0 5 0 0
T265 0 5 0 0
T273 0 5 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%