Module Definition
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Line Coverage for Module : tlul_err
Line No.TotalCoveredPercent
TOTAL262596.15
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN54100.00
ALWAYS571717100.00
CONT_ASSIGN9611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
32 1 1
36 1 1
39 1 1
42 1 1
54 0 1
57 1 1
58 1 1
59 1 1
61 1 1
62 1 1
64 1 1
65 1 1
66 1 1
70 1 1
72 1 1
74 1 1
78 1 1
79 1 1
80 1 1
90 1 1
91 1 1
92 1 1
96 1 1


Cond Coverage for Module : tlul_err
TotalCoveredPercent
Conditions352674.29
Logical352674.29
Non-Logical00
Event00

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT21,T22,T1

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------
-1--2--3-StatusTests
000CoveredT4,T5,T6
001Not Covered
010Not Covered
100CoveredT4,T5,T6

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------
-1--2--3-StatusTests
000Not Covered
001CoveredT4,T5,T6
010CoveredT21,T22,T1
100CoveredT4,T5,T6

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT21,T22,T1

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       72
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0CoveredT23,T24,T25
1Not Covered

 LINE       74
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0CoveredT23,T24,T25
1Not Covered

 LINE       96
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT4,T5,T6

 LINE       96
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT4,T5,T6
010CoveredT21,T22,T1
100CoveredT4,T5,T6

Branch Coverage for Module : tlul_err
Line No.TotalCoveredPercent
Branches 8 5 62.50
IF 61 8 5 62.50

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 61 if (tl_i.a_valid) -2-: 62 case (tl_i.a_size) -3-: 72 (tl_i.a_address[1]) ? -4-: 74 (tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Covered T23,T24,T25
1 'h1 1 - Not Covered
1 'h1 0 - Covered T23,T24,T25
1 'h1 - 1 Not Covered
1 'h1 - 0 Covered T23,T24,T25
1 'h00000002 - - Covered T4,T5,T6
1 default - - Not Covered
0 - - - Covered T4,T5,T6


Assert Coverage for Module : tlul_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 3692 3692 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3692 3692 0 0
T4 4 4 0 0
T5 4 4 0 0
T6 4 4 0 0
T18 4 4 0 0
T19 4 4 0 0
T62 4 4 0 0
T67 4 4 0 0
T68 4 4 0 0
T69 4 4 0 0
T72 4 4 0 0

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