Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T90,T1,T91
0	1	Covered	T90,T91,T318
1	0	Covered	T1

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T90,T1,T91
1	Covered	T90,T1,T91

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T90,T1,T91
1	Covered	T90,T1,T91

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T90,T91,T318
1	1	Covered	T90,T1,T91

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T90,T1,T91
1	0	Covered	T90,T1,T91
1	1	Covered	T90,T91,T318

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T90,T1,T91

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T90,T1,T91
0	Covered	T90,T1,T91

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T90,T1,T91
0	Covered	T90,T1,T91

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	790744728	776227044	0	0
CheckNGreaterZero_A	1846	1846	0	0
GntImpliesReady_A	790744728	8453	0	0
GntImpliesValid_A	790744728	8453	0	0
GrantKnown_A	790744728	776227044	0	0
IdxKnown_A	790744728	776227044	0	0
IndexIsCorrect_A	790744728	8453	0	0
NoReadyValidNoGrant_A	790744728	0	0	0
Priority_A	790744728	8453	0	0
ReadyAndValidImplyGrant_A	790744728	8453	0	0
ReqAndReadyImplyGrant_A	790744728	8453	0	0
ReqImpliesValid_A	790744728	8453	0	0
ValidKnown_A	790744728	776227044	0	0
gen_data_port_assertion.DataFlow_A	790744728	8453	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790744728	776227044	0	0
T4	523866	523632	0	0
T5	334736	334612	0	0
T6	469296	469056	0	0
T18	605222	604784	0	0
T19	195544	195442	0	0
T62	463160	462934	0	0
T67	333028	332912	0	0
T68	144042	143932	0	0
T69	1833038	1831796	0	0
T72	314938	314714	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1846	1846	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T62	2	2	0	0
T67	2	2	0	0
T68	2	2	0	0
T69	2	2	0	0
T72	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790744728	8453	0	0
T22	221324	0	0	0
T58	746488	0	0	0
T90	173774	2817	0	0
T91	0	2816	0	0
T128	1846020	0	0	0
T129	377526	0	0	0
T154	495806	0	0	0
T179	510494	0	0	0
T196	167234	0	0	0
T262	458648	0	0	0
T318	0	2820	0	0
T348	309266	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790744728	8453	0	0
T22	221324	0	0	0
T58	746488	0	0	0
T90	173774	2817	0	0
T91	0	2816	0	0
T128	1846020	0	0	0
T129	377526	0	0	0
T154	495806	0	0	0
T179	510494	0	0	0
T196	167234	0	0	0
T262	458648	0	0	0
T318	0	2820	0	0
T348	309266	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790744728	776227044	0	0
T4	523866	523632	0	0
T5	334736	334612	0	0
T6	469296	469056	0	0
T18	605222	604784	0	0
T19	195544	195442	0	0
T62	463160	462934	0	0
T67	333028	332912	0	0
T68	144042	143932	0	0
T69	1833038	1831796	0	0
T72	314938	314714	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790744728	776227044	0	0
T4	523866	523632	0	0
T5	334736	334612	0	0
T6	469296	469056	0	0
T18	605222	604784	0	0
T19	195544	195442	0	0
T62	463160	462934	0	0
T67	333028	332912	0	0
T68	144042	143932	0	0
T69	1833038	1831796	0	0
T72	314938	314714	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790744728	8453	0	0
T22	221324	0	0	0
T58	746488	0	0	0
T90	173774	2817	0	0
T91	0	2816	0	0
T128	1846020	0	0	0
T129	377526	0	0	0
T154	495806	0	0	0
T179	510494	0	0	0
T196	167234	0	0	0
T262	458648	0	0	0
T318	0	2820	0	0
T348	309266	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790744728	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790744728	8453	0	0
T22	221324	0	0	0
T58	746488	0	0	0
T90	173774	2817	0	0
T91	0	2816	0	0
T128	1846020	0	0	0
T129	377526	0	0	0
T154	495806	0	0	0
T179	510494	0	0	0
T196	167234	0	0	0
T262	458648	0	0	0
T318	0	2820	0	0
T348	309266	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790744728	8453	0	0
T22	221324	0	0	0
T58	746488	0	0	0
T90	173774	2817	0	0
T91	0	2816	0	0
T128	1846020	0	0	0
T129	377526	0	0	0
T154	495806	0	0	0
T179	510494	0	0	0
T196	167234	0	0	0
T262	458648	0	0	0
T318	0	2820	0	0
T348	309266	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790744728	8453	0	0
T22	221324	0	0	0
T58	746488	0	0	0
T90	173774	2817	0	0
T91	0	2816	0	0
T128	1846020	0	0	0
T129	377526	0	0	0
T154	495806	0	0	0
T179	510494	0	0	0
T196	167234	0	0	0
T262	458648	0	0	0
T318	0	2820	0	0
T348	309266	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790744728	8453	0	0
T22	221324	0	0	0
T58	746488	0	0	0
T90	173774	2817	0	0
T91	0	2816	0	0
T128	1846020	0	0	0
T129	377526	0	0	0
T154	495806	0	0	0
T179	510494	0	0	0
T196	167234	0	0	0
T262	458648	0	0	0
T318	0	2820	0	0
T348	309266	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790744728	776227044	0	0
T4	523866	523632	0	0
T5	334736	334612	0	0
T6	469296	469056	0	0
T18	605222	604784	0	0
T19	195544	195442	0	0
T62	463160	462934	0	0
T67	333028	332912	0	0
T68	144042	143932	0	0
T69	1833038	1831796	0	0
T72	314938	314714	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790744728	8453	0	0
T22	221324	0	0	0
T58	746488	0	0	0
T90	173774	2817	0	0
T91	0	2816	0	0
T128	1846020	0	0	0
T129	377526	0	0	0
T154	495806	0	0	0
T179	510494	0	0	0
T196	167234	0	0	0
T262	458648	0	0	0
T318	0	2820	0	0
T348	309266	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T90,T1,T91
0	1	Covered	T90,T91,T318
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T90,T91,T318
1	Covered	T90,T1,T91

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T90,T91,T318
1	Covered	T90,T1,T91

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T90,T91,T318
1	1	Covered	T90,T91,T318

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T90,T1,T91
1	0	Covered	T90,T91,T318
1	1	Covered	T90,T91,T318

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T90,T91,T318

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T90,T1,T91
0	Covered	T90,T91,T318

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T90,T1,T91
0	Covered	T90,T91,T318

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395372364	388113522	0	0
CheckNGreaterZero_A	923	923	0	0
GntImpliesReady_A	395372364	5270	0	0
GntImpliesValid_A	395372364	5270	0	0
GrantKnown_A	395372364	388113522	0	0
IdxKnown_A	395372364	388113522	0	0
IndexIsCorrect_A	395372364	5270	0	0
NoReadyValidNoGrant_A	395372364	0	0	0
Priority_A	395372364	5270	0	0
ReadyAndValidImplyGrant_A	395372364	5270	0	0
ReqAndReadyImplyGrant_A	395372364	5270	0	0
ReqImpliesValid_A	395372364	5270	0	0
ValidKnown_A	395372364	388113522	0	0
gen_data_port_assertion.DataFlow_A	395372364	5270	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	388113522	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	5270	0	0
T22	110662	0	0	0
T58	373244	0	0	0
T90	86887	1756	0	0
T91	0	1755	0	0
T128	923010	0	0	0
T129	188763	0	0	0
T154	247903	0	0	0
T179	255247	0	0	0
T196	83617	0	0	0
T262	229324	0	0	0
T318	0	1759	0	0
T348	154633	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	5270	0	0
T22	110662	0	0	0
T58	373244	0	0	0
T90	86887	1756	0	0
T91	0	1755	0	0
T128	923010	0	0	0
T129	188763	0	0	0
T154	247903	0	0	0
T179	255247	0	0	0
T196	83617	0	0	0
T262	229324	0	0	0
T318	0	1759	0	0
T348	154633	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	388113522	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	388113522	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	5270	0	0
T22	110662	0	0	0
T58	373244	0	0	0
T90	86887	1756	0	0
T91	0	1755	0	0
T128	923010	0	0	0
T129	188763	0	0	0
T154	247903	0	0	0
T179	255247	0	0	0
T196	83617	0	0	0
T262	229324	0	0	0
T318	0	1759	0	0
T348	154633	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	5270	0	0
T22	110662	0	0	0
T58	373244	0	0	0
T90	86887	1756	0	0
T91	0	1755	0	0
T128	923010	0	0	0
T129	188763	0	0	0
T154	247903	0	0	0
T179	255247	0	0	0
T196	83617	0	0	0
T262	229324	0	0	0
T318	0	1759	0	0
T348	154633	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	5270	0	0
T22	110662	0	0	0
T58	373244	0	0	0
T90	86887	1756	0	0
T91	0	1755	0	0
T128	923010	0	0	0
T129	188763	0	0	0
T154	247903	0	0	0
T179	255247	0	0	0
T196	83617	0	0	0
T262	229324	0	0	0
T318	0	1759	0	0
T348	154633	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	5270	0	0
T22	110662	0	0	0
T58	373244	0	0	0
T90	86887	1756	0	0
T91	0	1755	0	0
T128	923010	0	0	0
T129	188763	0	0	0
T154	247903	0	0	0
T179	255247	0	0	0
T196	83617	0	0	0
T262	229324	0	0	0
T318	0	1759	0	0
T348	154633	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	5270	0	0
T22	110662	0	0	0
T58	373244	0	0	0
T90	86887	1756	0	0
T91	0	1755	0	0
T128	923010	0	0	0
T129	188763	0	0	0
T154	247903	0	0	0
T179	255247	0	0	0
T196	83617	0	0	0
T262	229324	0	0	0
T318	0	1759	0	0
T348	154633	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	388113522	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	5270	0	0
T22	110662	0	0	0
T58	373244	0	0	0
T90	86887	1756	0	0
T91	0	1755	0	0
T128	923010	0	0	0
T129	188763	0	0	0
T154	247903	0	0	0
T179	255247	0	0	0
T196	83617	0	0	0
T262	229324	0	0	0
T318	0	1759	0	0
T348	154633	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T90,T1,T91
0	1	Covered	T90,T91,T318
1	0	Covered	T1

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T90,T1,T91
1	Covered	T90,T1,T91

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T90,T1,T91
1	Covered	T90,T1,T91

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T90,T91,T318
1	1	Covered	T90,T1,T91

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T90,T1,T91
1	0	Covered	T90,T1,T91
1	1	Covered	T90,T91,T318

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T90,T1,T91

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T90,T1,T91
0	Covered	T90,T1,T91

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T90,T1,T91
0	Covered	T90,T1,T91

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395372364	388113522	0	0
CheckNGreaterZero_A	923	923	0	0
GntImpliesReady_A	395372364	3183	0	0
GntImpliesValid_A	395372364	3183	0	0
GrantKnown_A	395372364	388113522	0	0
IdxKnown_A	395372364	388113522	0	0
IndexIsCorrect_A	395372364	3183	0	0
NoReadyValidNoGrant_A	395372364	0	0	0
Priority_A	395372364	3183	0	0
ReadyAndValidImplyGrant_A	395372364	3183	0	0
ReqAndReadyImplyGrant_A	395372364	3183	0	0
ReqImpliesValid_A	395372364	3183	0	0
ValidKnown_A	395372364	388113522	0	0
gen_data_port_assertion.DataFlow_A	395372364	3183	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	388113522	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	3183	0	0
T22	110662	0	0	0
T58	373244	0	0	0
T90	86887	1061	0	0
T91	0	1061	0	0
T128	923010	0	0	0
T129	188763	0	0	0
T154	247903	0	0	0
T179	255247	0	0	0
T196	83617	0	0	0
T262	229324	0	0	0
T318	0	1061	0	0
T348	154633	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	3183	0	0
T22	110662	0	0	0
T58	373244	0	0	0
T90	86887	1061	0	0
T91	0	1061	0	0
T128	923010	0	0	0
T129	188763	0	0	0
T154	247903	0	0	0
T179	255247	0	0	0
T196	83617	0	0	0
T262	229324	0	0	0
T318	0	1061	0	0
T348	154633	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	388113522	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	388113522	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	3183	0	0
T22	110662	0	0	0
T58	373244	0	0	0
T90	86887	1061	0	0
T91	0	1061	0	0
T128	923010	0	0	0
T129	188763	0	0	0
T154	247903	0	0	0
T179	255247	0	0	0
T196	83617	0	0	0
T262	229324	0	0	0
T318	0	1061	0	0
T348	154633	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	3183	0	0
T22	110662	0	0	0
T58	373244	0	0	0
T90	86887	1061	0	0
T91	0	1061	0	0
T128	923010	0	0	0
T129	188763	0	0	0
T154	247903	0	0	0
T179	255247	0	0	0
T196	83617	0	0	0
T262	229324	0	0	0
T318	0	1061	0	0
T348	154633	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	3183	0	0
T22	110662	0	0	0
T58	373244	0	0	0
T90	86887	1061	0	0
T91	0	1061	0	0
T128	923010	0	0	0
T129	188763	0	0	0
T154	247903	0	0	0
T179	255247	0	0	0
T196	83617	0	0	0
T262	229324	0	0	0
T318	0	1061	0	0
T348	154633	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	3183	0	0
T22	110662	0	0	0
T58	373244	0	0	0
T90	86887	1061	0	0
T91	0	1061	0	0
T128	923010	0	0	0
T129	188763	0	0	0
T154	247903	0	0	0
T179	255247	0	0	0
T196	83617	0	0	0
T262	229324	0	0	0
T318	0	1061	0	0
T348	154633	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	3183	0	0
T22	110662	0	0	0
T58	373244	0	0	0
T90	86887	1061	0	0
T91	0	1061	0	0
T128	923010	0	0	0
T129	188763	0	0	0
T154	247903	0	0	0
T179	255247	0	0	0
T196	83617	0	0	0
T262	229324	0	0	0
T318	0	1061	0	0
T348	154633	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	388113522	0	0
T4	261933	261816	0	0
T5	167368	167306	0	0
T6	234648	234528	0	0
T18	302611	302392	0	0
T19	97772	97721	0	0
T62	231580	231467	0	0
T67	166514	166456	0	0
T68	72021	71966	0	0
T69	916519	915898	0	0
T72	157469	157357	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	3183	0	0
T22	110662	0	0	0
T58	373244	0	0	0
T90	86887	1061	0	0
T91	0	1061	0	0
T128	923010	0	0	0
T129	188763	0	0	0
T154	247903	0	0	0
T179	255247	0	0	0
T196	83617	0	0	0
T262	229324	0	0	0
T318	0	1061	0	0
T348	154633	0	0	0