| T543 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.4133430180 |
|
|
May 28 04:05:27 PM PDT 24 |
May 28 04:22:58 PM PDT 24 |
5975142303 ps |
| T102 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.846254465 |
|
|
May 28 03:52:46 PM PDT 24 |
May 28 04:00:49 PM PDT 24 |
4098607600 ps |
| T473 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.310587345 |
|
|
May 28 04:22:48 PM PDT 24 |
May 28 04:28:46 PM PDT 24 |
3381281730 ps |
| T362 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1209640164 |
|
|
May 28 03:55:31 PM PDT 24 |
May 28 04:20:43 PM PDT 24 |
10964263227 ps |
| T346 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3399260189 |
|
|
May 28 03:43:04 PM PDT 24 |
May 28 03:54:08 PM PDT 24 |
4326608430 ps |
| T544 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2752367879 |
|
|
May 28 04:27:24 PM PDT 24 |
May 28 04:36:49 PM PDT 24 |
4770818600 ps |
| T429 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.2218108111 |
|
|
May 28 04:24:32 PM PDT 24 |
May 28 04:32:52 PM PDT 24 |
5275880828 ps |
| T402 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1598889299 |
|
|
May 28 03:44:56 PM PDT 24 |
May 28 04:55:07 PM PDT 24 |
17327883400 ps |
| T304 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.461587668 |
|
|
May 28 04:18:49 PM PDT 24 |
May 28 04:27:39 PM PDT 24 |
4578753250 ps |
| T85 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2313799865 |
|
|
May 28 04:20:51 PM PDT 24 |
May 28 04:26:28 PM PDT 24 |
3883165370 ps |
| T133 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.624622729 |
|
|
May 28 04:12:51 PM PDT 24 |
May 28 04:22:09 PM PDT 24 |
4204723440 ps |
| T385 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2002494491 |
|
|
May 28 04:27:03 PM PDT 24 |
May 28 04:33:08 PM PDT 24 |
3995787988 ps |
| T386 |
/workspace/coverage/default/2.chip_sw_aes_idle.846843089 |
|
|
May 28 04:08:34 PM PDT 24 |
May 28 04:13:16 PM PDT 24 |
2908411832 ps |
| T387 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.736899876 |
|
|
May 28 03:53:35 PM PDT 24 |
May 28 04:02:47 PM PDT 24 |
3941093808 ps |
| T212 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2574335075 |
|
|
May 28 04:02:17 PM PDT 24 |
May 28 04:13:14 PM PDT 24 |
4956817748 ps |
| T388 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4287972454 |
|
|
May 28 03:57:15 PM PDT 24 |
May 28 05:02:33 PM PDT 24 |
14607066612 ps |
| T389 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.2840806490 |
|
|
May 28 04:18:37 PM PDT 24 |
May 28 04:45:24 PM PDT 24 |
9315596590 ps |
| T390 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1082457376 |
|
|
May 28 03:53:17 PM PDT 24 |
May 28 04:02:10 PM PDT 24 |
5615184896 ps |
| T352 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2656535109 |
|
|
May 28 03:47:27 PM PDT 24 |
May 28 04:17:58 PM PDT 24 |
8287433678 ps |
| T545 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.3164374812 |
|
|
May 28 03:44:05 PM PDT 24 |
May 28 04:03:16 PM PDT 24 |
6211278360 ps |
| T546 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3031811513 |
|
|
May 28 04:08:18 PM PDT 24 |
May 28 04:24:14 PM PDT 24 |
6795999792 ps |
| T547 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.774401695 |
|
|
May 28 03:43:44 PM PDT 24 |
May 28 04:02:36 PM PDT 24 |
8321377520 ps |
| T548 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.3947960309 |
|
|
May 28 03:54:12 PM PDT 24 |
May 28 04:06:47 PM PDT 24 |
4231159944 ps |
| T549 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2898476465 |
|
|
May 28 04:20:33 PM PDT 24 |
May 28 04:27:14 PM PDT 24 |
3314940300 ps |
| T44 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2367188065 |
|
|
May 28 03:46:14 PM PDT 24 |
May 28 04:11:23 PM PDT 24 |
11483671904 ps |
| T380 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3234508370 |
|
|
May 28 04:13:23 PM PDT 24 |
May 28 04:21:58 PM PDT 24 |
4785461036 ps |
| T183 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3119230640 |
|
|
May 28 04:00:49 PM PDT 24 |
May 28 04:30:57 PM PDT 24 |
13186451408 ps |
| T28 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.98144045 |
|
|
May 28 03:46:10 PM PDT 24 |
May 28 03:55:37 PM PDT 24 |
5313246582 ps |
| T70 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2002135717 |
|
|
May 28 03:56:34 PM PDT 24 |
May 28 05:47:04 PM PDT 24 |
21549928608 ps |
| T550 |
/workspace/coverage/default/0.chip_sw_example_flash.1907911885 |
|
|
May 28 03:42:01 PM PDT 24 |
May 28 03:46:16 PM PDT 24 |
3048936800 ps |
| T145 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2264012960 |
|
|
May 28 03:47:29 PM PDT 24 |
May 28 03:58:07 PM PDT 24 |
6341803272 ps |
| T551 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.4175175505 |
|
|
May 28 04:04:40 PM PDT 24 |
May 28 04:10:03 PM PDT 24 |
2462936960 ps |
| T552 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.43450248 |
|
|
May 28 04:16:49 PM PDT 24 |
May 28 04:45:49 PM PDT 24 |
8522665700 ps |
| T422 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2639145340 |
|
|
May 28 04:28:47 PM PDT 24 |
May 28 04:36:11 PM PDT 24 |
5963986136 ps |
| T382 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.55752153 |
|
|
May 28 04:25:09 PM PDT 24 |
May 28 04:31:59 PM PDT 24 |
3018976312 ps |
| T553 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.4141053370 |
|
|
May 28 03:46:12 PM PDT 24 |
May 28 03:51:11 PM PDT 24 |
3341050708 ps |
| T350 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.900148055 |
|
|
May 28 04:06:40 PM PDT 24 |
May 28 04:17:25 PM PDT 24 |
3695302630 ps |
| T292 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.3923100867 |
|
|
May 28 03:56:38 PM PDT 24 |
May 28 04:55:26 PM PDT 24 |
28486178073 ps |
| T143 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4168704813 |
|
|
May 28 04:12:32 PM PDT 24 |
May 28 04:19:29 PM PDT 24 |
4872111432 ps |
| T231 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2346311503 |
|
|
May 28 03:59:34 PM PDT 24 |
May 28 04:37:06 PM PDT 24 |
8529051590 ps |
| T554 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.1186806063 |
|
|
May 28 04:04:16 PM PDT 24 |
May 28 04:42:48 PM PDT 24 |
10215079904 ps |
| T439 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3129723006 |
|
|
May 28 04:20:15 PM PDT 24 |
May 28 04:26:53 PM PDT 24 |
4017071568 ps |
| T9 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.848219110 |
|
|
May 28 04:01:59 PM PDT 24 |
May 28 04:08:29 PM PDT 24 |
6617543088 ps |
| T78 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.292677182 |
|
|
May 28 04:12:17 PM PDT 24 |
May 28 04:21:12 PM PDT 24 |
3370094062 ps |
| T555 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2125983435 |
|
|
May 28 04:17:42 PM PDT 24 |
May 28 04:29:16 PM PDT 24 |
4324805720 ps |
| T218 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1831940179 |
|
|
May 28 03:52:26 PM PDT 24 |
May 28 03:57:39 PM PDT 24 |
2636899560 ps |
| T377 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.3111385644 |
|
|
May 28 04:24:12 PM PDT 24 |
May 28 04:34:57 PM PDT 24 |
4692249856 ps |
| T240 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1031673659 |
|
|
May 28 03:55:21 PM PDT 24 |
May 28 04:06:51 PM PDT 24 |
5383091120 ps |
| T363 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1223523341 |
|
|
May 28 04:11:52 PM PDT 24 |
May 28 04:18:25 PM PDT 24 |
2954671570 ps |
| T250 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1433982628 |
|
|
May 28 04:11:03 PM PDT 24 |
May 28 04:23:33 PM PDT 24 |
5150149639 ps |
| T15 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1559610615 |
|
|
May 28 04:00:43 PM PDT 24 |
May 28 04:35:29 PM PDT 24 |
20666851250 ps |
| T556 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3960907645 |
|
|
May 28 03:53:34 PM PDT 24 |
May 28 03:58:22 PM PDT 24 |
3183244392 ps |
| T305 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1817263411 |
|
|
May 28 04:08:53 PM PDT 24 |
May 28 04:17:41 PM PDT 24 |
3639055296 ps |
| T557 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2543439025 |
|
|
May 28 03:59:05 PM PDT 24 |
May 28 04:06:34 PM PDT 24 |
6599399786 ps |
| T558 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.773767045 |
|
|
May 28 04:18:06 PM PDT 24 |
May 28 04:37:00 PM PDT 24 |
9302520008 ps |
| T559 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3098339893 |
|
|
May 28 04:08:13 PM PDT 24 |
May 28 05:09:13 PM PDT 24 |
14234494451 ps |
| T126 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3240953345 |
|
|
May 28 04:11:34 PM PDT 24 |
May 28 04:17:10 PM PDT 24 |
3202529014 ps |
| T127 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2066649834 |
|
|
May 28 04:00:45 PM PDT 24 |
May 28 04:05:41 PM PDT 24 |
2842212346 ps |
| T560 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.447187934 |
|
|
May 28 03:59:20 PM PDT 24 |
May 28 04:04:08 PM PDT 24 |
3330435219 ps |
| T110 |
/workspace/coverage/default/0.chip_sw_gpio.793461074 |
|
|
May 28 03:42:26 PM PDT 24 |
May 28 03:49:09 PM PDT 24 |
4059907172 ps |
| T284 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1643082076 |
|
|
May 28 03:53:45 PM PDT 24 |
May 28 03:58:13 PM PDT 24 |
3420995834 ps |
| T336 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2610202572 |
|
|
May 28 03:46:24 PM PDT 24 |
May 28 03:53:14 PM PDT 24 |
4730084076 ps |
| T561 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.366554686 |
|
|
May 28 03:52:31 PM PDT 24 |
May 28 03:57:48 PM PDT 24 |
3191545544 ps |
| T562 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2221666623 |
|
|
May 28 03:55:21 PM PDT 24 |
May 28 05:05:46 PM PDT 24 |
14279636514 ps |
| T458 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1310337916 |
|
|
May 28 04:20:57 PM PDT 24 |
May 28 04:27:09 PM PDT 24 |
4022475762 ps |
| T563 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3634759620 |
|
|
May 28 03:57:53 PM PDT 24 |
May 28 05:10:21 PM PDT 24 |
14831390008 ps |
| T45 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2549574015 |
|
|
May 28 04:08:49 PM PDT 24 |
May 28 04:30:07 PM PDT 24 |
10127025960 ps |
| T347 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3074766692 |
|
|
May 28 04:08:15 PM PDT 24 |
May 28 04:20:27 PM PDT 24 |
18845161448 ps |
| T564 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.2892289796 |
|
|
May 28 03:57:41 PM PDT 24 |
May 28 04:57:20 PM PDT 24 |
13645180063 ps |
| T490 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2743815097 |
|
|
May 28 04:24:12 PM PDT 24 |
May 28 04:29:04 PM PDT 24 |
3676140648 ps |
| T155 |
/workspace/coverage/default/2.chip_sw_alert_test.1076367192 |
|
|
May 28 04:08:20 PM PDT 24 |
May 28 04:13:42 PM PDT 24 |
2626332848 ps |
| T565 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.4170938527 |
|
|
May 28 03:44:02 PM PDT 24 |
May 28 03:48:33 PM PDT 24 |
3033420056 ps |
| T17 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2284842736 |
|
|
May 28 03:53:45 PM PDT 24 |
May 28 03:59:44 PM PDT 24 |
5075191048 ps |
| T478 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3162939302 |
|
|
May 28 04:25:25 PM PDT 24 |
May 28 04:36:07 PM PDT 24 |
4955563196 ps |
| T413 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1877299219 |
|
|
May 28 04:26:06 PM PDT 24 |
May 28 04:34:33 PM PDT 24 |
4890350668 ps |
| T103 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.1413877025 |
|
|
May 28 03:42:31 PM PDT 24 |
May 28 03:50:22 PM PDT 24 |
3439711504 ps |
| T200 |
/workspace/coverage/default/2.chip_jtag_mem_access.2061570910 |
|
|
May 28 04:05:51 PM PDT 24 |
May 28 04:33:53 PM PDT 24 |
13471080950 ps |
| T503 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3943865287 |
|
|
May 28 04:18:55 PM PDT 24 |
May 28 04:25:01 PM PDT 24 |
3057126728 ps |
| T463 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2422094156 |
|
|
May 28 04:21:37 PM PDT 24 |
May 28 04:29:17 PM PDT 24 |
3900035000 ps |
| T566 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.496292561 |
|
|
May 28 04:19:42 PM PDT 24 |
May 28 04:49:09 PM PDT 24 |
8849724264 ps |
| T567 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2827105727 |
|
|
May 28 04:03:09 PM PDT 24 |
May 28 04:28:10 PM PDT 24 |
7408401334 ps |
| T568 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2217085775 |
|
|
May 28 04:23:26 PM PDT 24 |
May 28 04:31:16 PM PDT 24 |
4241665248 ps |
| T306 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1910795049 |
|
|
May 28 04:18:14 PM PDT 24 |
May 28 04:29:31 PM PDT 24 |
5331221896 ps |
| T569 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.160866673 |
|
|
May 28 04:04:23 PM PDT 24 |
May 28 04:14:11 PM PDT 24 |
4012317796 ps |
| T570 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2558273978 |
|
|
May 28 03:59:51 PM PDT 24 |
May 28 04:11:38 PM PDT 24 |
5608421750 ps |
| T571 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3967937512 |
|
|
May 28 04:12:14 PM PDT 24 |
May 28 04:15:24 PM PDT 24 |
2631077515 ps |
| T364 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3340696082 |
|
|
May 28 03:58:09 PM PDT 24 |
May 28 04:50:34 PM PDT 24 |
34014963768 ps |
| T572 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2191992447 |
|
|
May 28 04:01:01 PM PDT 24 |
May 28 04:11:13 PM PDT 24 |
4894041104 ps |
| T151 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3695294292 |
|
|
May 28 03:42:03 PM PDT 24 |
May 28 03:49:51 PM PDT 24 |
3678767476 ps |
| T573 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1040691294 |
|
|
May 28 04:12:53 PM PDT 24 |
May 28 04:22:32 PM PDT 24 |
5474354400 ps |
| T574 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3539751688 |
|
|
May 28 04:04:22 PM PDT 24 |
May 28 04:08:40 PM PDT 24 |
2904897472 ps |
| T199 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1133527681 |
|
|
May 28 04:12:51 PM PDT 24 |
May 28 04:18:34 PM PDT 24 |
5200117200 ps |
| T575 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2412207063 |
|
|
May 28 04:15:26 PM PDT 24 |
May 28 04:18:58 PM PDT 24 |
3218014872 ps |
| T576 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1117289256 |
|
|
May 28 03:56:27 PM PDT 24 |
May 28 04:13:54 PM PDT 24 |
7634553856 ps |
| T577 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2215425459 |
|
|
May 28 04:09:40 PM PDT 24 |
May 28 04:19:30 PM PDT 24 |
5920029834 ps |
| T79 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.4049108637 |
|
|
May 28 03:49:18 PM PDT 24 |
May 28 03:58:37 PM PDT 24 |
4317779980 ps |
| T383 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2210323796 |
|
|
May 28 04:26:30 PM PDT 24 |
May 28 04:34:42 PM PDT 24 |
4228817668 ps |
| T207 |
/workspace/coverage/default/1.chip_sw_flash_init.613679023 |
|
|
May 28 03:54:07 PM PDT 24 |
May 28 04:29:08 PM PDT 24 |
20038979336 ps |
| T39 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.1005635038 |
|
|
May 28 04:12:59 PM PDT 24 |
May 28 04:23:56 PM PDT 24 |
6165315978 ps |
| T152 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1866991224 |
|
|
May 28 03:53:54 PM PDT 24 |
May 28 04:17:32 PM PDT 24 |
11905505838 ps |
| T208 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.4217262820 |
|
|
May 28 04:14:32 PM PDT 24 |
May 28 04:40:53 PM PDT 24 |
20406556193 ps |
| T12 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.1423998406 |
|
|
May 28 04:04:31 PM PDT 24 |
May 28 04:07:59 PM PDT 24 |
3228317844 ps |
| T440 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3490275459 |
|
|
May 28 04:22:41 PM PDT 24 |
May 28 04:29:43 PM PDT 24 |
3808235960 ps |
| T578 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.1910503829 |
|
|
May 28 04:01:53 PM PDT 24 |
May 28 04:07:53 PM PDT 24 |
3026454680 ps |
| T579 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.570181928 |
|
|
May 28 03:55:25 PM PDT 24 |
May 28 04:47:50 PM PDT 24 |
13696418102 ps |
| T580 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1690298874 |
|
|
May 28 04:14:48 PM PDT 24 |
May 28 04:20:02 PM PDT 24 |
4893248131 ps |
| T581 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3910928177 |
|
|
May 28 04:17:15 PM PDT 24 |
May 28 04:28:37 PM PDT 24 |
4309221792 ps |
| T582 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.4239026170 |
|
|
May 28 04:00:29 PM PDT 24 |
May 28 04:04:30 PM PDT 24 |
2747898990 ps |
| T465 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3774793491 |
|
|
May 28 04:19:49 PM PDT 24 |
May 28 04:25:37 PM PDT 24 |
3791254784 ps |
| T356 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2122486830 |
|
|
May 28 03:47:17 PM PDT 24 |
May 28 04:18:40 PM PDT 24 |
7549526040 ps |
| T583 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1896384779 |
|
|
May 28 03:47:08 PM PDT 24 |
May 28 03:59:35 PM PDT 24 |
7112347680 ps |
| T448 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.366975582 |
|
|
May 28 04:24:15 PM PDT 24 |
May 28 04:31:20 PM PDT 24 |
3529201244 ps |
| T40 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.2864101774 |
|
|
May 28 04:02:53 PM PDT 24 |
May 28 04:10:07 PM PDT 24 |
5204004280 ps |
| T584 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2220812470 |
|
|
May 28 03:56:08 PM PDT 24 |
May 28 04:20:34 PM PDT 24 |
9206397012 ps |
| T585 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1900776131 |
|
|
May 28 04:18:22 PM PDT 24 |
May 28 04:29:07 PM PDT 24 |
3818203538 ps |
| T117 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.362658788 |
|
|
May 28 04:02:11 PM PDT 24 |
May 28 04:09:58 PM PDT 24 |
4795183160 ps |
| T586 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.1561793724 |
|
|
May 28 04:24:10 PM PDT 24 |
May 28 04:33:30 PM PDT 24 |
4422187340 ps |
| T587 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.153991723 |
|
|
May 28 04:27:24 PM PDT 24 |
May 28 04:37:58 PM PDT 24 |
5232614776 ps |
| T170 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2039867106 |
|
|
May 28 04:13:28 PM PDT 24 |
May 28 04:20:06 PM PDT 24 |
7136751208 ps |
| T206 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.862958076 |
|
|
May 28 04:03:01 PM PDT 24 |
May 28 04:36:36 PM PDT 24 |
27268915115 ps |
| T588 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.53332504 |
|
|
May 28 04:00:45 PM PDT 24 |
May 28 04:33:08 PM PDT 24 |
8085910522 ps |
| T106 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1767405481 |
|
|
May 28 04:13:06 PM PDT 24 |
May 28 04:58:31 PM PDT 24 |
20529847903 ps |
| T468 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.2840194875 |
|
|
May 28 04:24:09 PM PDT 24 |
May 28 04:31:49 PM PDT 24 |
4129857954 ps |
| T497 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2842255180 |
|
|
May 28 04:24:13 PM PDT 24 |
May 28 04:29:20 PM PDT 24 |
3304274090 ps |
| T589 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.2082504830 |
|
|
May 28 03:59:16 PM PDT 24 |
May 28 04:28:47 PM PDT 24 |
8522451296 ps |
| T276 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2610348245 |
|
|
May 28 03:44:23 PM PDT 24 |
May 28 03:53:36 PM PDT 24 |
6217742948 ps |
| T225 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.957635871 |
|
|
May 28 03:48:49 PM PDT 24 |
May 28 04:07:08 PM PDT 24 |
7022349848 ps |
| T590 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.762838429 |
|
|
May 28 04:04:17 PM PDT 24 |
May 28 04:08:07 PM PDT 24 |
2932182322 ps |
| T591 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.1531298516 |
|
|
May 28 03:57:03 PM PDT 24 |
May 28 04:01:57 PM PDT 24 |
3111331260 ps |
| T592 |
/workspace/coverage/default/0.chip_sw_kmac_idle.2701389895 |
|
|
May 28 03:48:35 PM PDT 24 |
May 28 03:53:37 PM PDT 24 |
2665978312 ps |
| T322 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.2026169932 |
|
|
May 28 04:02:43 PM PDT 24 |
May 28 04:11:12 PM PDT 24 |
10005943618 ps |
| T309 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.2475599741 |
|
|
May 28 04:25:25 PM PDT 24 |
May 28 04:37:23 PM PDT 24 |
4713149468 ps |
| T310 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.822242996 |
|
|
May 28 04:21:51 PM PDT 24 |
May 28 04:30:46 PM PDT 24 |
4521714574 ps |
| T593 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.938682628 |
|
|
May 28 03:58:14 PM PDT 24 |
May 28 04:24:01 PM PDT 24 |
8358233856 ps |
| T594 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.2812581780 |
|
|
May 28 04:05:29 PM PDT 24 |
May 28 04:10:49 PM PDT 24 |
2861749384 ps |
| T595 |
/workspace/coverage/default/0.chip_tap_straps_dev.3105468017 |
|
|
May 28 03:48:39 PM PDT 24 |
May 28 04:19:35 PM PDT 24 |
18182569460 ps |
| T596 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.669032346 |
|
|
May 28 04:21:32 PM PDT 24 |
May 28 04:54:49 PM PDT 24 |
12896992520 ps |
| T597 |
/workspace/coverage/default/1.chip_sw_aes_idle.3385172846 |
|
|
May 28 04:03:01 PM PDT 24 |
May 28 04:05:48 PM PDT 24 |
2959254740 ps |
| T598 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.3532530097 |
|
|
May 28 03:47:34 PM PDT 24 |
May 28 03:52:27 PM PDT 24 |
3500879845 ps |
| T599 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1362868143 |
|
|
May 28 03:52:36 PM PDT 24 |
May 28 03:58:51 PM PDT 24 |
2996506270 ps |
| T113 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.681434230 |
|
|
May 28 04:05:46 PM PDT 24 |
May 28 04:10:04 PM PDT 24 |
2960533328 ps |
| T35 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2450296722 |
|
|
May 28 03:48:51 PM PDT 24 |
May 28 03:57:51 PM PDT 24 |
4988365900 ps |
| T146 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1373308094 |
|
|
May 28 04:00:05 PM PDT 24 |
May 28 04:19:53 PM PDT 24 |
9377546850 ps |
| T600 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1593643935 |
|
|
May 28 04:19:15 PM PDT 24 |
May 28 04:58:13 PM PDT 24 |
13299233752 ps |
| T411 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3967850860 |
|
|
May 28 04:22:37 PM PDT 24 |
May 28 04:28:30 PM PDT 24 |
3055379650 ps |
| T601 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3030073349 |
|
|
May 28 04:12:52 PM PDT 24 |
May 28 04:23:51 PM PDT 24 |
4276100448 ps |
| T434 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.122135456 |
|
|
May 28 04:26:59 PM PDT 24 |
May 28 04:33:14 PM PDT 24 |
3760089382 ps |
| T454 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2890416724 |
|
|
May 28 04:27:52 PM PDT 24 |
May 28 04:39:20 PM PDT 24 |
5997193100 ps |
| T602 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3851031014 |
|
|
May 28 03:59:23 PM PDT 24 |
May 28 04:18:40 PM PDT 24 |
6683692928 ps |
| T459 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3294069624 |
|
|
May 28 04:26:45 PM PDT 24 |
May 28 04:32:23 PM PDT 24 |
3883048024 ps |
| T603 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3260641109 |
|
|
May 28 03:55:26 PM PDT 24 |
May 28 04:52:36 PM PDT 24 |
13624127405 ps |
| T604 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.4001209350 |
|
|
May 28 03:45:11 PM PDT 24 |
May 28 04:55:26 PM PDT 24 |
18491364210 ps |
| T605 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2059194663 |
|
|
May 28 03:57:59 PM PDT 24 |
May 28 04:53:57 PM PDT 24 |
16842369396 ps |
| T435 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.3811878371 |
|
|
May 28 04:26:53 PM PDT 24 |
May 28 04:36:50 PM PDT 24 |
5343442664 ps |
| T606 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.835775482 |
|
|
May 28 04:00:14 PM PDT 24 |
May 28 04:26:26 PM PDT 24 |
7245187464 ps |
| T607 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3781588802 |
|
|
May 28 04:20:43 PM PDT 24 |
May 28 04:47:51 PM PDT 24 |
8603675004 ps |
| T608 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1770588608 |
|
|
May 28 04:06:53 PM PDT 24 |
May 28 04:19:04 PM PDT 24 |
3562206876 ps |
| T431 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1399906263 |
|
|
May 28 04:29:11 PM PDT 24 |
May 28 04:35:31 PM PDT 24 |
3791054060 ps |
| T450 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.3815054113 |
|
|
May 28 04:25:09 PM PDT 24 |
May 28 04:34:11 PM PDT 24 |
5898861544 ps |
| T609 |
/workspace/coverage/default/1.chip_sw_example_rom.404201205 |
|
|
May 28 03:52:00 PM PDT 24 |
May 28 03:53:53 PM PDT 24 |
2806108622 ps |
| T610 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1394176610 |
|
|
May 28 03:49:35 PM PDT 24 |
May 28 04:01:12 PM PDT 24 |
4692182360 ps |
| T611 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4026660921 |
|
|
May 28 03:49:05 PM PDT 24 |
May 28 03:54:36 PM PDT 24 |
3237916509 ps |
| T612 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3131051887 |
|
|
May 28 04:07:18 PM PDT 24 |
May 28 04:38:07 PM PDT 24 |
17143312467 ps |
| T613 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3620461822 |
|
|
May 28 04:02:11 PM PDT 24 |
May 28 04:12:43 PM PDT 24 |
3836323328 ps |
| T285 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1800260969 |
|
|
May 28 04:27:12 PM PDT 24 |
May 28 04:37:14 PM PDT 24 |
5279605530 ps |
| T114 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.737350060 |
|
|
May 28 03:44:07 PM PDT 24 |
May 28 03:49:08 PM PDT 24 |
3484896624 ps |
| T614 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1967462167 |
|
|
May 28 03:58:57 PM PDT 24 |
May 28 05:05:24 PM PDT 24 |
13495481184 ps |
| T436 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.171243824 |
|
|
May 28 04:24:10 PM PDT 24 |
May 28 04:30:46 PM PDT 24 |
3644799666 ps |
| T615 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3300182101 |
|
|
May 28 04:14:17 PM PDT 24 |
May 28 04:18:35 PM PDT 24 |
2823772539 ps |
| T616 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.2387147824 |
|
|
May 28 03:58:48 PM PDT 24 |
May 28 04:02:46 PM PDT 24 |
2841798552 ps |
| T617 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2587884339 |
|
|
May 28 04:00:57 PM PDT 24 |
May 28 04:14:07 PM PDT 24 |
4650686288 ps |
| T618 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.125842593 |
|
|
May 28 04:06:05 PM PDT 24 |
May 28 04:27:13 PM PDT 24 |
7748337104 ps |
| T148 |
/workspace/coverage/default/4.chip_tap_straps_rma.564649845 |
|
|
May 28 04:17:46 PM PDT 24 |
May 28 04:21:25 PM PDT 24 |
3201301022 ps |
| T281 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2921420640 |
|
|
May 28 03:58:18 PM PDT 24 |
May 28 05:32:19 PM PDT 24 |
22529356312 ps |
| T466 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.902967672 |
|
|
May 28 04:18:21 PM PDT 24 |
May 28 04:24:56 PM PDT 24 |
3930196944 ps |
| T619 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.4018431729 |
|
|
May 28 04:08:49 PM PDT 24 |
May 28 04:59:22 PM PDT 24 |
10225541119 ps |
| T620 |
/workspace/coverage/default/1.chip_sw_kmac_idle.2244470462 |
|
|
May 28 04:02:29 PM PDT 24 |
May 28 04:06:47 PM PDT 24 |
3133461000 ps |
| T492 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.518007761 |
|
|
May 28 04:29:28 PM PDT 24 |
May 28 04:35:31 PM PDT 24 |
3652181584 ps |
| T415 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3695087716 |
|
|
May 28 04:28:17 PM PDT 24 |
May 28 04:38:24 PM PDT 24 |
4710242910 ps |
| T256 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.533243357 |
|
|
May 28 03:49:54 PM PDT 24 |
May 28 03:58:48 PM PDT 24 |
4100430750 ps |
| T505 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1095998311 |
|
|
May 28 04:22:43 PM PDT 24 |
May 28 04:29:06 PM PDT 24 |
3512804194 ps |
| T392 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2910198578 |
|
|
May 28 03:48:54 PM PDT 24 |
May 28 03:54:25 PM PDT 24 |
3309795604 ps |
| T209 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.1638076386 |
|
|
May 28 04:00:31 PM PDT 24 |
May 28 04:18:56 PM PDT 24 |
5950902032 ps |
| T621 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3924324701 |
|
|
May 28 04:09:11 PM PDT 24 |
May 28 04:20:20 PM PDT 24 |
5547036958 ps |
| T622 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.285012302 |
|
|
May 28 03:55:42 PM PDT 24 |
May 28 05:06:21 PM PDT 24 |
13291051400 ps |
| T623 |
/workspace/coverage/default/2.chip_tap_straps_dev.2769712603 |
|
|
May 28 04:13:42 PM PDT 24 |
May 28 04:16:35 PM PDT 24 |
2749338798 ps |
| T272 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.3406632435 |
|
|
May 28 04:00:17 PM PDT 24 |
May 28 04:07:02 PM PDT 24 |
4400119064 ps |
| T624 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.382279415 |
|
|
May 28 03:47:29 PM PDT 24 |
May 28 04:05:35 PM PDT 24 |
5642604830 ps |
| T625 |
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2803022195 |
|
|
May 28 04:19:27 PM PDT 24 |
May 28 05:39:18 PM PDT 24 |
20439480066 ps |
| T626 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.462055122 |
|
|
May 28 03:42:02 PM PDT 24 |
May 28 03:52:07 PM PDT 24 |
4437286116 ps |
| T627 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.2470593297 |
|
|
May 28 03:59:30 PM PDT 24 |
May 28 04:03:53 PM PDT 24 |
2508100360 ps |
| T178 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3782795005 |
|
|
May 28 04:17:10 PM PDT 24 |
May 28 04:25:23 PM PDT 24 |
8171888890 ps |
| T628 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3707835785 |
|
|
May 28 04:08:41 PM PDT 24 |
May 28 04:42:08 PM PDT 24 |
24465825191 ps |
| T629 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1523276853 |
|
|
May 28 03:52:03 PM PDT 24 |
May 28 04:02:17 PM PDT 24 |
4056239478 ps |
| T149 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.1017970967 |
|
|
May 28 04:15:30 PM PDT 24 |
May 28 04:20:42 PM PDT 24 |
3817018041 ps |
| T630 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3849894573 |
|
|
May 28 04:19:44 PM PDT 24 |
May 28 05:17:39 PM PDT 24 |
14541180548 ps |
| T631 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.3248031108 |
|
|
May 28 03:52:26 PM PDT 24 |
May 28 03:58:12 PM PDT 24 |
3098592000 ps |
| T632 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3393870312 |
|
|
May 28 03:48:02 PM PDT 24 |
May 28 03:58:21 PM PDT 24 |
4009662408 ps |
| T633 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.1788386836 |
|
|
May 28 04:19:21 PM PDT 24 |
May 28 04:29:51 PM PDT 24 |
5556541378 ps |
| T634 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.3357911836 |
|
|
May 28 04:19:19 PM PDT 24 |
May 28 05:08:09 PM PDT 24 |
14132885298 ps |
| T635 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2535819257 |
|
|
May 28 03:54:53 PM PDT 24 |
May 28 04:03:16 PM PDT 24 |
3683104740 ps |
| T636 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.2565780015 |
|
|
May 28 03:59:00 PM PDT 24 |
May 28 04:05:12 PM PDT 24 |
3192313424 ps |
| T370 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.628658158 |
|
|
May 28 03:58:56 PM PDT 24 |
May 28 04:10:35 PM PDT 24 |
4847394384 ps |
| T637 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1846460597 |
|
|
May 28 04:19:11 PM PDT 24 |
May 28 05:15:58 PM PDT 24 |
14070602361 ps |
| T638 |
/workspace/coverage/default/2.chip_sw_power_idle_load.303337136 |
|
|
May 28 04:14:58 PM PDT 24 |
May 28 04:29:40 PM PDT 24 |
3950699996 ps |
| T351 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2492599339 |
|
|
May 28 03:44:34 PM PDT 24 |
May 28 03:56:15 PM PDT 24 |
3943521432 ps |
| T639 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2714286314 |
|
|
May 28 03:56:46 PM PDT 24 |
May 28 04:58:38 PM PDT 24 |
13888562680 ps |
| T640 |
/workspace/coverage/default/0.chip_sw_hmac_enc.228178945 |
|
|
May 28 03:47:45 PM PDT 24 |
May 28 03:51:41 PM PDT 24 |
2811709050 ps |
| T641 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.463478399 |
|
|
May 28 03:45:58 PM PDT 24 |
May 28 03:51:33 PM PDT 24 |
3252641546 ps |
| T471 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1306515076 |
|
|
May 28 04:27:59 PM PDT 24 |
May 28 04:38:25 PM PDT 24 |
5555704056 ps |
| T286 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.2261268989 |
|
|
May 28 04:21:07 PM PDT 24 |
May 28 04:30:19 PM PDT 24 |
4868690296 ps |
| T642 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.3111389411 |
|
|
May 28 03:47:15 PM PDT 24 |
May 28 03:51:28 PM PDT 24 |
3435796480 ps |
| T643 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1717755792 |
|
|
May 28 04:00:41 PM PDT 24 |
May 28 04:11:02 PM PDT 24 |
3713969360 ps |
| T287 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.663898757 |
|
|
May 28 04:06:51 PM PDT 24 |
May 28 04:17:36 PM PDT 24 |
5770290974 ps |
| T397 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3080460486 |
|
|
May 28 03:51:03 PM PDT 24 |
May 28 04:53:06 PM PDT 24 |
24127298289 ps |
| T412 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.1922174011 |
|
|
May 28 04:20:05 PM PDT 24 |
May 28 04:30:30 PM PDT 24 |
5663234028 ps |
| T644 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2038192996 |
|
|
May 28 04:00:30 PM PDT 24 |
May 28 04:21:47 PM PDT 24 |
8647618154 ps |
| T645 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2173640958 |
|
|
May 28 03:47:02 PM PDT 24 |
May 28 04:17:22 PM PDT 24 |
7680294620 ps |
| T477 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1034147970 |
|
|
May 28 04:25:43 PM PDT 24 |
May 28 04:32:21 PM PDT 24 |
3860097968 ps |
| T464 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3653164429 |
|
|
May 28 04:19:57 PM PDT 24 |
May 28 04:27:00 PM PDT 24 |
3795135450 ps |
| T202 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2077973101 |
|
|
May 28 03:44:34 PM PDT 24 |
May 28 03:58:44 PM PDT 24 |
6891846582 ps |
| T646 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.2264541271 |
|
|
May 28 03:49:02 PM PDT 24 |
May 28 04:10:45 PM PDT 24 |
6429681928 ps |
| T455 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.67299054 |
|
|
May 28 04:17:59 PM PDT 24 |
May 28 04:26:02 PM PDT 24 |
3528281816 ps |
| T333 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.788260902 |
|
|
May 28 04:00:37 PM PDT 24 |
May 28 05:09:33 PM PDT 24 |
17525892080 ps |
| T94 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.353583785 |
|
|
May 28 03:55:39 PM PDT 24 |
May 28 04:00:47 PM PDT 24 |
3755984910 ps |
| T29 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3337156768 |
|
|
May 28 04:00:53 PM PDT 24 |
May 28 04:09:51 PM PDT 24 |
6182205568 ps |
| T647 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2437198222 |
|
|
May 28 04:09:29 PM PDT 24 |
May 28 04:14:32 PM PDT 24 |
3831781273 ps |
| T648 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1716440054 |
|
|
May 28 04:03:56 PM PDT 24 |
May 28 04:10:18 PM PDT 24 |
3140880990 ps |
| T649 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3008651570 |
|
|
May 28 04:04:02 PM PDT 24 |
May 28 04:09:45 PM PDT 24 |
4408863454 ps |
| T230 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.342104692 |
|
|
May 28 04:05:01 PM PDT 24 |
May 28 04:16:34 PM PDT 24 |
4735747000 ps |
| T650 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3594802575 |
|
|
May 28 04:29:46 PM PDT 24 |
May 28 04:38:05 PM PDT 24 |
6098189952 ps |
| T651 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.4223576298 |
|
|
May 28 03:44:09 PM PDT 24 |
May 28 03:49:44 PM PDT 24 |
4580646196 ps |
| T652 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.4191963300 |
|
|
May 28 04:17:50 PM PDT 24 |
May 28 04:42:52 PM PDT 24 |
7986801080 ps |
| T229 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.4164898030 |
|
|
May 28 04:06:29 PM PDT 24 |
May 28 04:37:19 PM PDT 24 |
11665162146 ps |
| T460 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2702200374 |
|
|
May 28 04:26:14 PM PDT 24 |
May 28 04:32:13 PM PDT 24 |
3530762552 ps |
| T487 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3546449848 |
|
|
May 28 04:30:09 PM PDT 24 |
May 28 04:36:12 PM PDT 24 |
3292434622 ps |
| T653 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.25198388 |
|
|
May 28 04:11:57 PM PDT 24 |
May 28 04:44:25 PM PDT 24 |
23015460854 ps |
| T479 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2342313681 |
|
|
May 28 04:24:22 PM PDT 24 |
May 28 04:29:30 PM PDT 24 |
2980809408 ps |
| T398 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.591355134 |
|
|
May 28 03:59:59 PM PDT 24 |
May 28 06:04:33 PM PDT 24 |
26698377624 ps |
| T282 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.854929517 |
|
|
May 28 03:58:17 PM PDT 24 |
May 28 05:38:51 PM PDT 24 |
21833322432 ps |
| T184 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.689136851 |
|
|
May 28 03:59:15 PM PDT 24 |
May 28 04:04:42 PM PDT 24 |
2974661632 ps |
| T654 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2104674815 |
|
|
May 28 04:14:17 PM PDT 24 |
May 28 04:18:28 PM PDT 24 |
2664265011 ps |
| T655 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2706989573 |
|
|
May 28 04:22:02 PM PDT 24 |
May 28 04:30:10 PM PDT 24 |
4107897950 ps |
| T480 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.2412849818 |
|
|
May 28 04:25:14 PM PDT 24 |
May 28 04:37:07 PM PDT 24 |
4300151738 ps |
| T656 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.902311221 |
|
|
May 28 04:07:31 PM PDT 24 |
May 28 04:17:29 PM PDT 24 |
4160437044 ps |
| T366 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.999049692 |
|
|
May 28 03:52:39 PM PDT 24 |
May 28 04:04:59 PM PDT 24 |
5022124352 ps |
| T657 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3643213933 |
|
|
May 28 03:55:47 PM PDT 24 |
May 28 04:01:54 PM PDT 24 |
3942358139 ps |
| T658 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.4223860868 |
|
|
May 28 04:12:51 PM PDT 24 |
May 28 04:21:01 PM PDT 24 |
2991753160 ps |
| T307 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1073788092 |
|
|
May 28 03:42:34 PM PDT 24 |
May 28 03:55:43 PM PDT 24 |
5373080212 ps |
| T659 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.760001511 |
|
|
May 28 04:02:53 PM PDT 24 |
May 28 04:07:32 PM PDT 24 |
3330795110 ps |