| T660 |
/workspace/coverage/default/3.chip_tap_straps_rma.528107736 |
|
|
May 28 04:16:26 PM PDT 24 |
May 28 04:21:49 PM PDT 24 |
4097453635 ps |
| T210 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.3690687085 |
|
|
May 28 03:48:54 PM PDT 24 |
May 28 04:09:23 PM PDT 24 |
5956382232 ps |
| T269 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1076060932 |
|
|
May 28 04:07:02 PM PDT 24 |
May 28 04:11:38 PM PDT 24 |
2993801734 ps |
| T661 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.170123782 |
|
|
May 28 04:07:31 PM PDT 24 |
May 28 04:15:43 PM PDT 24 |
4567098820 ps |
| T662 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1039112975 |
|
|
May 28 03:59:58 PM PDT 24 |
May 28 04:11:23 PM PDT 24 |
8532149548 ps |
| T663 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.763631648 |
|
|
May 28 04:03:20 PM PDT 24 |
May 28 04:18:29 PM PDT 24 |
7507832934 ps |
| T432 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2595217487 |
|
|
May 28 04:25:52 PM PDT 24 |
May 28 04:34:57 PM PDT 24 |
4912586896 ps |
| T475 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.839660300 |
|
|
May 28 03:42:06 PM PDT 24 |
May 28 03:55:17 PM PDT 24 |
5674735414 ps |
| T353 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.64954347 |
|
|
May 28 04:00:04 PM PDT 24 |
May 28 04:24:01 PM PDT 24 |
6650465400 ps |
| T664 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.379861333 |
|
|
May 28 04:18:20 PM PDT 24 |
May 28 04:21:46 PM PDT 24 |
2566006540 ps |
| T433 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3548831906 |
|
|
May 28 04:25:35 PM PDT 24 |
May 28 04:34:04 PM PDT 24 |
3716148772 ps |
| T665 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.931508430 |
|
|
May 28 03:45:50 PM PDT 24 |
May 28 03:55:13 PM PDT 24 |
4441296820 ps |
| T666 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.3390426545 |
|
|
May 28 04:16:26 PM PDT 24 |
May 28 04:32:28 PM PDT 24 |
6927147750 ps |
| T369 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1230108702 |
|
|
May 28 03:50:13 PM PDT 24 |
May 28 03:54:06 PM PDT 24 |
3088872442 ps |
| T204 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1069581998 |
|
|
May 28 03:58:54 PM PDT 24 |
May 28 04:30:03 PM PDT 24 |
23209102067 ps |
| T667 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.551658441 |
|
|
May 28 04:20:27 PM PDT 24 |
May 28 04:58:03 PM PDT 24 |
12582747560 ps |
| T668 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3817549445 |
|
|
May 28 03:55:46 PM PDT 24 |
May 28 04:08:54 PM PDT 24 |
4200665963 ps |
| T327 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.514481548 |
|
|
May 28 03:53:59 PM PDT 24 |
May 28 03:57:29 PM PDT 24 |
2625461000 ps |
| T251 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3402923812 |
|
|
May 28 03:56:53 PM PDT 24 |
May 28 04:08:41 PM PDT 24 |
4300101855 ps |
| T669 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4067956399 |
|
|
May 28 03:48:07 PM PDT 24 |
May 28 03:59:09 PM PDT 24 |
3998027752 ps |
| T670 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.78199555 |
|
|
May 28 04:13:59 PM PDT 24 |
May 28 04:24:35 PM PDT 24 |
3996479960 ps |
| T671 |
/workspace/coverage/default/0.chip_sw_power_idle_load.4112074027 |
|
|
May 28 04:00:45 PM PDT 24 |
May 28 04:12:50 PM PDT 24 |
4309236920 ps |
| T416 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1752760864 |
|
|
May 28 04:26:26 PM PDT 24 |
May 28 04:33:22 PM PDT 24 |
3732695136 ps |
| T496 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1113777691 |
|
|
May 28 04:24:32 PM PDT 24 |
May 28 04:36:12 PM PDT 24 |
5123286036 ps |
| T672 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.2155407397 |
|
|
May 28 04:25:46 PM PDT 24 |
May 28 04:38:10 PM PDT 24 |
5889357336 ps |
| T673 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1699120530 |
|
|
May 28 03:45:23 PM PDT 24 |
May 28 04:11:48 PM PDT 24 |
10600216873 ps |
| T288 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3144123137 |
|
|
May 28 04:27:57 PM PDT 24 |
May 28 04:36:26 PM PDT 24 |
4842807020 ps |
| T119 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.1544577830 |
|
|
May 28 04:08:26 PM PDT 24 |
May 28 04:15:46 PM PDT 24 |
3714902968 ps |
| T674 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.504164879 |
|
|
May 28 03:54:47 PM PDT 24 |
May 28 03:59:59 PM PDT 24 |
2823485468 ps |
| T675 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.1108409001 |
|
|
May 28 03:59:56 PM PDT 24 |
May 28 04:03:00 PM PDT 24 |
2002019736 ps |
| T676 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.1068356584 |
|
|
May 28 03:56:27 PM PDT 24 |
May 28 04:14:13 PM PDT 24 |
5604309946 ps |
| T677 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2644006549 |
|
|
May 28 03:47:12 PM PDT 24 |
May 28 04:35:14 PM PDT 24 |
12695003160 ps |
| T235 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.4093569769 |
|
|
May 28 03:54:24 PM PDT 24 |
May 28 04:05:59 PM PDT 24 |
4129053330 ps |
| T678 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.204061551 |
|
|
May 28 04:02:40 PM PDT 24 |
May 28 04:20:09 PM PDT 24 |
7315839210 ps |
| T679 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.509754591 |
|
|
May 28 03:43:42 PM PDT 24 |
May 28 03:46:49 PM PDT 24 |
2858886668 ps |
| T391 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1233613859 |
|
|
May 28 03:58:51 PM PDT 24 |
May 28 04:20:24 PM PDT 24 |
11924654564 ps |
| T680 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2456489899 |
|
|
May 28 03:56:12 PM PDT 24 |
May 28 05:08:35 PM PDT 24 |
15029951048 ps |
| T681 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.1150292041 |
|
|
May 28 03:45:55 PM PDT 24 |
May 28 03:51:05 PM PDT 24 |
3154824800 ps |
| T682 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3755386242 |
|
|
May 28 03:59:55 PM PDT 24 |
May 28 04:06:31 PM PDT 24 |
4396936020 ps |
| T683 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.4278142175 |
|
|
May 28 04:19:22 PM PDT 24 |
May 28 04:28:11 PM PDT 24 |
4087880600 ps |
| T684 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.2904500331 |
|
|
May 28 04:16:15 PM PDT 24 |
May 28 04:21:31 PM PDT 24 |
2876626698 ps |
| T150 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.2453304618 |
|
|
May 28 04:01:36 PM PDT 24 |
May 28 04:07:22 PM PDT 24 |
3978015419 ps |
| T367 |
/workspace/coverage/default/2.chip_sival_flash_info_access.38380798 |
|
|
May 28 04:05:40 PM PDT 24 |
May 28 04:11:19 PM PDT 24 |
3417117512 ps |
| T685 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.326660917 |
|
|
May 28 03:43:26 PM PDT 24 |
May 28 04:02:58 PM PDT 24 |
5387375029 ps |
| T686 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3829479740 |
|
|
May 28 04:18:24 PM PDT 24 |
May 28 05:50:30 PM PDT 24 |
21983795820 ps |
| T687 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1047736676 |
|
|
May 28 03:49:33 PM PDT 24 |
May 28 03:57:51 PM PDT 24 |
3974030748 ps |
| T688 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.1147778201 |
|
|
May 28 04:15:23 PM PDT 24 |
May 28 04:21:09 PM PDT 24 |
2995434226 ps |
| T689 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2246686259 |
|
|
May 28 04:00:26 PM PDT 24 |
May 28 04:05:05 PM PDT 24 |
2489565544 ps |
| T120 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.4094116963 |
|
|
May 28 03:58:10 PM PDT 24 |
May 28 04:04:31 PM PDT 24 |
2991315326 ps |
| T485 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1149008505 |
|
|
May 28 04:26:11 PM PDT 24 |
May 28 04:33:11 PM PDT 24 |
4125674124 ps |
| T407 |
/workspace/coverage/default/3.chip_tap_straps_dev.2687988256 |
|
|
May 28 04:17:11 PM PDT 24 |
May 28 04:28:10 PM PDT 24 |
6078458127 ps |
| T690 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.284063726 |
|
|
May 28 04:12:43 PM PDT 24 |
May 28 04:16:13 PM PDT 24 |
2470671000 ps |
| T691 |
/workspace/coverage/default/2.chip_sw_example_flash.1325501576 |
|
|
May 28 04:05:28 PM PDT 24 |
May 28 04:08:49 PM PDT 24 |
2707190712 ps |
| T692 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2555383642 |
|
|
May 28 03:52:51 PM PDT 24 |
May 28 03:58:52 PM PDT 24 |
5512000194 ps |
| T693 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3025014365 |
|
|
May 28 04:17:37 PM PDT 24 |
May 28 04:22:08 PM PDT 24 |
2904370004 ps |
| T493 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.248632491 |
|
|
May 28 04:20:56 PM PDT 24 |
May 28 04:26:42 PM PDT 24 |
3857051656 ps |
| T694 |
/workspace/coverage/default/1.chip_sw_edn_kat.1293284008 |
|
|
May 28 04:01:20 PM PDT 24 |
May 28 04:12:24 PM PDT 24 |
3827509750 ps |
| T695 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1205996908 |
|
|
May 28 03:57:24 PM PDT 24 |
May 28 05:11:35 PM PDT 24 |
17768371681 ps |
| T696 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2391446640 |
|
|
May 28 04:12:20 PM PDT 24 |
May 28 04:22:07 PM PDT 24 |
3875082500 ps |
| T405 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1676542691 |
|
|
May 28 04:16:21 PM PDT 24 |
May 28 04:27:14 PM PDT 24 |
5024927634 ps |
| T697 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3878100689 |
|
|
May 28 04:06:13 PM PDT 24 |
May 28 04:16:42 PM PDT 24 |
4324255240 ps |
| T252 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.311020880 |
|
|
May 28 03:56:52 PM PDT 24 |
May 28 04:01:31 PM PDT 24 |
3341940981 ps |
| T698 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1865787913 |
|
|
May 28 04:00:24 PM PDT 24 |
May 28 04:11:41 PM PDT 24 |
4547663942 ps |
| T699 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2594098611 |
|
|
May 28 04:20:22 PM PDT 24 |
May 28 05:48:13 PM PDT 24 |
24805499800 ps |
| T700 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.1088321757 |
|
|
May 28 04:08:34 PM PDT 24 |
May 28 04:12:48 PM PDT 24 |
2671265925 ps |
| T701 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3115351041 |
|
|
May 28 03:53:48 PM PDT 24 |
May 28 04:04:34 PM PDT 24 |
4575838066 ps |
| T702 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1970190758 |
|
|
May 28 04:00:41 PM PDT 24 |
May 28 04:23:40 PM PDT 24 |
6595109186 ps |
| T449 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1747199171 |
|
|
May 28 04:19:33 PM PDT 24 |
May 28 04:25:23 PM PDT 24 |
3840372522 ps |
| T703 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2213492584 |
|
|
May 28 04:12:30 PM PDT 24 |
May 28 04:20:50 PM PDT 24 |
7641570186 ps |
| T704 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.372296410 |
|
|
May 28 03:59:16 PM PDT 24 |
May 28 04:15:47 PM PDT 24 |
5398566188 ps |
| T10 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.625969525 |
|
|
May 28 04:01:04 PM PDT 24 |
May 28 04:28:12 PM PDT 24 |
18760485360 ps |
| T705 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.4183721148 |
|
|
May 28 04:28:03 PM PDT 24 |
May 28 04:33:38 PM PDT 24 |
3096525860 ps |
| T446 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.918197586 |
|
|
May 28 04:25:20 PM PDT 24 |
May 28 04:31:11 PM PDT 24 |
3509426280 ps |
| T443 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.924633128 |
|
|
May 28 04:22:51 PM PDT 24 |
May 28 04:29:44 PM PDT 24 |
3431284368 ps |
| T7 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.4182692979 |
|
|
May 28 04:13:09 PM PDT 24 |
May 28 04:19:52 PM PDT 24 |
3004368438 ps |
| T706 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1671610759 |
|
|
May 28 03:55:54 PM PDT 24 |
May 28 05:07:46 PM PDT 24 |
14570336676 ps |
| T494 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1951725781 |
|
|
May 28 04:27:19 PM PDT 24 |
May 28 04:38:06 PM PDT 24 |
4721643424 ps |
| T707 |
/workspace/coverage/default/0.chip_sw_edn_kat.1673486077 |
|
|
May 28 03:46:40 PM PDT 24 |
May 28 03:56:22 PM PDT 24 |
3454553864 ps |
| T293 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3745591945 |
|
|
May 28 03:54:23 PM PDT 24 |
May 28 04:06:03 PM PDT 24 |
4772097912 ps |
| T294 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.844371718 |
|
|
May 28 04:02:37 PM PDT 24 |
May 28 04:10:55 PM PDT 24 |
4872161536 ps |
| T295 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2550315795 |
|
|
May 28 03:47:50 PM PDT 24 |
May 28 03:58:17 PM PDT 24 |
4183728846 ps |
| T296 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.1927936120 |
|
|
May 28 03:42:11 PM PDT 24 |
May 28 03:45:10 PM PDT 24 |
3049752460 ps |
| T297 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3916798337 |
|
|
May 28 04:23:51 PM PDT 24 |
May 28 04:32:21 PM PDT 24 |
3980092568 ps |
| T298 |
/workspace/coverage/default/3.chip_tap_straps_prod.1688957672 |
|
|
May 28 04:17:38 PM PDT 24 |
May 28 04:20:07 PM PDT 24 |
2794898673 ps |
| T299 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1309381958 |
|
|
May 28 04:14:16 PM PDT 24 |
May 28 04:27:38 PM PDT 24 |
4132378420 ps |
| T300 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.5832250 |
|
|
May 28 04:22:12 PM PDT 24 |
May 28 04:33:06 PM PDT 24 |
5927136568 ps |
| T301 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3519105521 |
|
|
May 28 03:46:38 PM PDT 24 |
May 28 04:19:23 PM PDT 24 |
8794302948 ps |
| T302 |
/workspace/coverage/default/0.chip_tap_straps_rma.532127570 |
|
|
May 28 03:49:06 PM PDT 24 |
May 28 03:55:55 PM PDT 24 |
5023506833 ps |
| T185 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2663491462 |
|
|
May 28 03:44:09 PM PDT 24 |
May 28 03:47:18 PM PDT 24 |
2605594072 ps |
| T708 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.2547384652 |
|
|
May 28 04:17:16 PM PDT 24 |
May 28 04:30:08 PM PDT 24 |
6286231160 ps |
| T709 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1455250440 |
|
|
May 28 04:22:33 PM PDT 24 |
May 28 04:30:10 PM PDT 24 |
3632924716 ps |
| T710 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1492083274 |
|
|
May 28 04:01:23 PM PDT 24 |
May 28 04:13:52 PM PDT 24 |
4293668524 ps |
| T378 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.1275728858 |
|
|
May 28 04:22:11 PM PDT 24 |
May 28 04:31:13 PM PDT 24 |
4429724674 ps |
| T253 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3600953441 |
|
|
May 28 03:46:38 PM PDT 24 |
May 28 03:53:53 PM PDT 24 |
3094073959 ps |
| T504 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.404931876 |
|
|
May 28 04:26:26 PM PDT 24 |
May 28 04:33:36 PM PDT 24 |
5231616094 ps |
| T711 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.44008106 |
|
|
May 28 04:10:31 PM PDT 24 |
May 28 04:14:12 PM PDT 24 |
3071906176 ps |
| T712 |
/workspace/coverage/default/0.chip_sival_flash_info_access.4046393865 |
|
|
May 28 03:42:24 PM PDT 24 |
May 28 03:48:18 PM PDT 24 |
2969745186 ps |
| T713 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.771368603 |
|
|
May 28 04:08:03 PM PDT 24 |
May 28 05:06:47 PM PDT 24 |
37515997261 ps |
| T714 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1154004395 |
|
|
May 28 04:16:57 PM PDT 24 |
May 28 04:52:17 PM PDT 24 |
10407559854 ps |
| T715 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2850407340 |
|
|
May 28 03:50:11 PM PDT 24 |
May 28 03:53:28 PM PDT 24 |
2614355361 ps |
| T716 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1238984381 |
|
|
May 28 03:57:42 PM PDT 24 |
May 28 04:46:43 PM PDT 24 |
10317063707 ps |
| T717 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.4199435718 |
|
|
May 28 04:05:47 PM PDT 24 |
May 28 04:27:16 PM PDT 24 |
8897895400 ps |
| T718 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1007870981 |
|
|
May 28 04:05:10 PM PDT 24 |
May 28 04:10:59 PM PDT 24 |
5316901216 ps |
| T161 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.256528680 |
|
|
May 28 04:18:22 PM PDT 24 |
May 28 04:28:46 PM PDT 24 |
4551832740 ps |
| T451 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2725566579 |
|
|
May 28 04:29:51 PM PDT 24 |
May 28 04:39:26 PM PDT 24 |
5964436984 ps |
| T719 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.579036246 |
|
|
May 28 04:17:59 PM PDT 24 |
May 28 04:26:56 PM PDT 24 |
4233604260 ps |
| T720 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2945716639 |
|
|
May 28 04:08:32 PM PDT 24 |
May 28 04:16:49 PM PDT 24 |
7174909672 ps |
| T721 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2701966307 |
|
|
May 28 04:18:20 PM PDT 24 |
May 28 04:40:35 PM PDT 24 |
8606300292 ps |
| T722 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3240915322 |
|
|
May 28 04:08:34 PM PDT 24 |
May 28 04:17:34 PM PDT 24 |
4323514920 ps |
| T723 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1165604508 |
|
|
May 28 03:47:42 PM PDT 24 |
May 28 03:50:37 PM PDT 24 |
2924005820 ps |
| T724 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2501574386 |
|
|
May 28 04:14:08 PM PDT 24 |
May 28 04:39:02 PM PDT 24 |
10662553741 ps |
| T725 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2077410546 |
|
|
May 28 04:07:37 PM PDT 24 |
May 28 04:18:19 PM PDT 24 |
6116672608 ps |
| T118 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1042875108 |
|
|
May 28 04:11:44 PM PDT 24 |
May 28 04:22:24 PM PDT 24 |
5746920574 ps |
| T726 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3358695975 |
|
|
May 28 04:09:07 PM PDT 24 |
May 28 05:10:56 PM PDT 24 |
15142344096 ps |
| T395 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1826288952 |
|
|
May 28 04:19:46 PM PDT 24 |
May 28 06:02:47 PM PDT 24 |
32134171416 ps |
| T727 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3788733868 |
|
|
May 28 04:01:50 PM PDT 24 |
May 28 04:12:13 PM PDT 24 |
4057427740 ps |
| T728 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2943656909 |
|
|
May 28 03:57:20 PM PDT 24 |
May 28 04:06:23 PM PDT 24 |
6760213500 ps |
| T498 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2621337513 |
|
|
May 28 04:22:39 PM PDT 24 |
May 28 04:30:02 PM PDT 24 |
3334320796 ps |
| T14 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1939430372 |
|
|
May 28 03:42:27 PM PDT 24 |
May 28 03:47:26 PM PDT 24 |
3730754232 ps |
| T121 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.895277801 |
|
|
May 28 03:43:09 PM PDT 24 |
May 28 03:49:08 PM PDT 24 |
3306439877 ps |
| T328 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.2694031785 |
|
|
May 28 03:54:52 PM PDT 24 |
May 28 06:59:25 PM PDT 24 |
65004726705 ps |
| T486 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1606643441 |
|
|
May 28 04:24:10 PM PDT 24 |
May 28 04:34:37 PM PDT 24 |
5120752624 ps |
| T729 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1363611918 |
|
|
May 28 04:22:53 PM PDT 24 |
May 28 04:28:21 PM PDT 24 |
3201951230 ps |
| T730 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.1427709868 |
|
|
May 28 03:53:18 PM PDT 24 |
May 28 03:56:15 PM PDT 24 |
3463835128 ps |
| T731 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3044710603 |
|
|
May 28 04:13:44 PM PDT 24 |
May 28 05:13:13 PM PDT 24 |
19716863483 ps |
| T461 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2133690885 |
|
|
May 28 04:18:21 PM PDT 24 |
May 28 04:25:24 PM PDT 24 |
3586078712 ps |
| T499 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2723402874 |
|
|
May 28 04:25:52 PM PDT 24 |
May 28 04:32:35 PM PDT 24 |
4555815400 ps |
| T408 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1880833359 |
|
|
May 28 04:08:11 PM PDT 24 |
May 28 04:22:15 PM PDT 24 |
4658939122 ps |
| T732 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.541380438 |
|
|
May 28 03:42:06 PM PDT 24 |
May 28 03:55:12 PM PDT 24 |
4455025294 ps |
| T733 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3746472604 |
|
|
May 28 04:13:27 PM PDT 24 |
May 28 05:18:31 PM PDT 24 |
16580794438 ps |
| T734 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3578842572 |
|
|
May 28 03:59:35 PM PDT 24 |
May 28 04:50:18 PM PDT 24 |
11557416932 ps |
| T735 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2469768092 |
|
|
May 28 03:49:14 PM PDT 24 |
May 28 03:59:35 PM PDT 24 |
4915129720 ps |
| T736 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1800730069 |
|
|
May 28 04:06:29 PM PDT 24 |
May 28 04:11:12 PM PDT 24 |
3108728889 ps |
| T737 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1537968734 |
|
|
May 28 04:11:22 PM PDT 24 |
May 28 06:06:58 PM PDT 24 |
27147740328 ps |
| T354 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.1372989159 |
|
|
May 28 04:11:47 PM PDT 24 |
May 28 04:36:02 PM PDT 24 |
7139196360 ps |
| T491 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4221582319 |
|
|
May 28 04:27:13 PM PDT 24 |
May 28 04:33:28 PM PDT 24 |
4349692464 ps |
| T738 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3233177257 |
|
|
May 28 03:55:20 PM PDT 24 |
May 28 04:15:38 PM PDT 24 |
5639460077 ps |
| T739 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2416744575 |
|
|
May 28 03:57:20 PM PDT 24 |
May 28 05:03:10 PM PDT 24 |
13924416641 ps |
| T147 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3196535097 |
|
|
May 28 04:13:04 PM PDT 24 |
May 28 04:26:05 PM PDT 24 |
6372596686 ps |
| T289 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2874439214 |
|
|
May 28 04:24:29 PM PDT 24 |
May 28 04:34:31 PM PDT 24 |
4379649188 ps |
| T740 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.779772398 |
|
|
May 28 04:27:41 PM PDT 24 |
May 28 04:36:57 PM PDT 24 |
5755956828 ps |
| T741 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1006277487 |
|
|
May 28 04:14:36 PM PDT 24 |
May 28 04:33:29 PM PDT 24 |
5858248360 ps |
| T399 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.1330868797 |
|
|
May 28 04:09:42 PM PDT 24 |
May 28 04:21:14 PM PDT 24 |
2979261432 ps |
| T742 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.250185191 |
|
|
May 28 04:11:13 PM PDT 24 |
May 28 04:15:48 PM PDT 24 |
2926648340 ps |
| T743 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.388287922 |
|
|
May 28 03:49:30 PM PDT 24 |
May 28 03:55:00 PM PDT 24 |
3106823372 ps |
| T744 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3099991204 |
|
|
May 28 04:19:07 PM PDT 24 |
May 28 04:31:37 PM PDT 24 |
4578859500 ps |
| T745 |
/workspace/coverage/default/0.chip_sw_aes_enc.3960041474 |
|
|
May 28 03:46:14 PM PDT 24 |
May 28 03:50:52 PM PDT 24 |
3157410210 ps |
| T746 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.918894755 |
|
|
May 28 04:21:49 PM PDT 24 |
May 28 05:08:41 PM PDT 24 |
14254316490 ps |
| T211 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.128568220 |
|
|
May 28 04:14:30 PM PDT 24 |
May 28 04:35:00 PM PDT 24 |
6038234000 ps |
| T747 |
/workspace/coverage/default/1.rom_keymgr_functest.3444501847 |
|
|
May 28 04:04:31 PM PDT 24 |
May 28 04:15:35 PM PDT 24 |
4557840490 ps |
| T748 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3689098540 |
|
|
May 28 04:00:04 PM PDT 24 |
May 28 04:40:11 PM PDT 24 |
10145332596 ps |
| T749 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.1675869834 |
|
|
May 28 04:03:52 PM PDT 24 |
May 28 04:07:31 PM PDT 24 |
2397863352 ps |
| T750 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.730995835 |
|
|
May 28 04:28:05 PM PDT 24 |
May 28 04:35:10 PM PDT 24 |
4257953592 ps |
| T751 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1635430880 |
|
|
May 28 03:45:12 PM PDT 24 |
May 28 03:56:47 PM PDT 24 |
7761919960 ps |
| T752 |
/workspace/coverage/default/1.chip_sw_aes_entropy.1625896908 |
|
|
May 28 03:59:32 PM PDT 24 |
May 28 04:03:42 PM PDT 24 |
2565475488 ps |
| T444 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2302832177 |
|
|
May 28 04:19:47 PM PDT 24 |
May 28 04:26:04 PM PDT 24 |
3317706120 ps |
| T753 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3997585616 |
|
|
May 28 04:12:25 PM PDT 24 |
May 28 04:21:46 PM PDT 24 |
5660908704 ps |
| T171 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2652858276 |
|
|
May 28 03:48:46 PM PDT 24 |
May 28 04:22:24 PM PDT 24 |
22461304764 ps |
| T754 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.233330337 |
|
|
May 28 04:19:25 PM PDT 24 |
May 28 05:26:41 PM PDT 24 |
14112610847 ps |
| T162 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2969102578 |
|
|
May 28 04:27:54 PM PDT 24 |
May 28 04:37:37 PM PDT 24 |
4961582262 ps |
| T755 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2082819836 |
|
|
May 28 03:58:05 PM PDT 24 |
May 28 04:04:23 PM PDT 24 |
6798220274 ps |
| T756 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.1532853084 |
|
|
May 28 04:16:49 PM PDT 24 |
May 28 04:19:54 PM PDT 24 |
2892080949 ps |
| T757 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2502327331 |
|
|
May 28 04:16:43 PM PDT 24 |
May 28 04:22:08 PM PDT 24 |
2997752280 ps |
| T758 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1598350718 |
|
|
May 28 03:58:27 PM PDT 24 |
May 28 04:05:11 PM PDT 24 |
3381730004 ps |
| T318 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1770100301 |
|
|
May 28 03:49:56 PM PDT 24 |
May 28 03:54:48 PM PDT 24 |
2894238208 ps |
| T759 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3181393703 |
|
|
May 28 04:11:23 PM PDT 24 |
May 28 04:17:10 PM PDT 24 |
3162555411 ps |
| T481 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.569134260 |
|
|
May 28 04:27:24 PM PDT 24 |
May 28 04:35:53 PM PDT 24 |
3968613346 ps |
| T760 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.2829330088 |
|
|
May 28 03:49:40 PM PDT 24 |
May 28 03:53:24 PM PDT 24 |
2749039143 ps |
| T761 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1660684344 |
|
|
May 28 04:04:01 PM PDT 24 |
May 28 04:22:34 PM PDT 24 |
5618438480 ps |
| T762 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.3605818234 |
|
|
May 28 04:00:47 PM PDT 24 |
May 28 04:23:46 PM PDT 24 |
4886971496 ps |
| T763 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3992408786 |
|
|
May 28 03:46:04 PM PDT 24 |
May 28 04:03:28 PM PDT 24 |
10036823800 ps |
| T764 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2878453903 |
|
|
May 28 03:46:40 PM PDT 24 |
May 28 03:50:06 PM PDT 24 |
3155270072 ps |
| T765 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.718564600 |
|
|
May 28 03:56:47 PM PDT 24 |
May 28 04:04:21 PM PDT 24 |
7957946140 ps |
| T441 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.614833835 |
|
|
May 28 04:27:50 PM PDT 24 |
May 28 04:39:33 PM PDT 24 |
4689190488 ps |
| T766 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.482685268 |
|
|
May 28 03:57:45 PM PDT 24 |
May 28 04:12:22 PM PDT 24 |
8350158914 ps |
| T261 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.1595700628 |
|
|
May 28 04:19:32 PM PDT 24 |
May 28 04:30:01 PM PDT 24 |
6318058252 ps |
| T767 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.387782874 |
|
|
May 28 04:05:20 PM PDT 24 |
May 28 04:17:58 PM PDT 24 |
4833557390 ps |
| T768 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1795486653 |
|
|
May 28 03:43:51 PM PDT 24 |
May 28 04:09:23 PM PDT 24 |
9028415346 ps |
| T769 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2409200360 |
|
|
May 28 03:46:08 PM PDT 24 |
May 28 03:52:08 PM PDT 24 |
3319400892 ps |
| T770 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.2449785272 |
|
|
May 28 03:48:50 PM PDT 24 |
May 28 03:52:37 PM PDT 24 |
3110423530 ps |
| T329 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3390984657 |
|
|
May 28 04:04:52 PM PDT 24 |
May 28 07:48:19 PM PDT 24 |
76930434205 ps |
| T771 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3100773040 |
|
|
May 28 04:16:20 PM PDT 24 |
May 28 04:20:51 PM PDT 24 |
2536480552 ps |
| T107 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.773292499 |
|
|
May 28 03:42:46 PM PDT 24 |
May 28 04:31:08 PM PDT 24 |
12136446316 ps |
| T772 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2791076440 |
|
|
May 28 04:11:04 PM PDT 24 |
May 28 04:15:32 PM PDT 24 |
3025031300 ps |
| T419 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.2539043414 |
|
|
May 28 04:23:44 PM PDT 24 |
May 28 04:34:01 PM PDT 24 |
5480339764 ps |
| T773 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.2345845931 |
|
|
May 28 04:10:25 PM PDT 24 |
May 28 04:45:50 PM PDT 24 |
8614484650 ps |
| T437 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1861322729 |
|
|
May 28 04:21:45 PM PDT 24 |
May 28 04:29:58 PM PDT 24 |
3746718950 ps |
| T774 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2036500658 |
|
|
May 28 03:57:27 PM PDT 24 |
May 28 04:04:50 PM PDT 24 |
4402482468 ps |
| T775 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3682908114 |
|
|
May 28 04:14:47 PM PDT 24 |
May 28 04:23:55 PM PDT 24 |
8920218232 ps |
| T776 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3103293198 |
|
|
May 28 03:47:32 PM PDT 24 |
May 28 03:54:50 PM PDT 24 |
5465575448 ps |
| T777 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.4081243913 |
|
|
May 28 04:16:05 PM PDT 24 |
May 28 04:26:22 PM PDT 24 |
5910959184 ps |
| T456 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.1372091156 |
|
|
May 28 04:25:16 PM PDT 24 |
May 28 04:34:37 PM PDT 24 |
5031602020 ps |
| T778 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.849470788 |
|
|
May 28 03:56:46 PM PDT 24 |
May 28 04:52:47 PM PDT 24 |
14093981336 ps |
| T779 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2884003204 |
|
|
May 28 03:46:45 PM PDT 24 |
May 28 03:54:58 PM PDT 24 |
2930691054 ps |
| T780 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3484234853 |
|
|
May 28 03:56:24 PM PDT 24 |
May 28 05:08:36 PM PDT 24 |
13640856624 ps |
| T781 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.4222478888 |
|
|
May 28 04:11:53 PM PDT 24 |
May 28 04:22:25 PM PDT 24 |
4956634005 ps |
| T782 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3301006770 |
|
|
May 28 04:24:47 PM PDT 24 |
May 28 04:35:31 PM PDT 24 |
4943398874 ps |
| T783 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.751061509 |
|
|
May 28 04:04:54 PM PDT 24 |
May 28 04:08:23 PM PDT 24 |
2879339960 ps |
| T784 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.3242101312 |
|
|
May 28 04:03:19 PM PDT 24 |
May 28 04:09:36 PM PDT 24 |
3091703520 ps |
| T379 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.3875484840 |
|
|
May 28 03:42:34 PM PDT 24 |
May 28 06:57:53 PM PDT 24 |
64614668383 ps |
| T785 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.4223740869 |
|
|
May 28 03:57:53 PM PDT 24 |
May 28 05:03:35 PM PDT 24 |
13937682628 ps |
| T365 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.3544801271 |
|
|
May 28 03:48:06 PM PDT 24 |
May 28 03:55:02 PM PDT 24 |
4044562562 ps |
| T786 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.789511440 |
|
|
May 28 03:46:18 PM PDT 24 |
May 28 04:49:38 PM PDT 24 |
20887808900 ps |
| T438 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.662209573 |
|
|
May 28 04:27:37 PM PDT 24 |
May 28 04:34:07 PM PDT 24 |
3143429016 ps |
| T787 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1407673382 |
|
|
May 28 04:01:58 PM PDT 24 |
May 28 04:05:45 PM PDT 24 |
2317369859 ps |
| T788 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.4283475820 |
|
|
May 28 04:20:39 PM PDT 24 |
May 28 04:31:31 PM PDT 24 |
6109244040 ps |
| T501 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.691538569 |
|
|
May 28 04:22:35 PM PDT 24 |
May 28 04:32:27 PM PDT 24 |
4742719380 ps |
| T180 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.139307451 |
|
|
May 28 04:06:28 PM PDT 24 |
May 28 04:15:05 PM PDT 24 |
4028158284 ps |
| T789 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3483174677 |
|
|
May 28 04:08:33 PM PDT 24 |
May 28 05:15:28 PM PDT 24 |
14449864912 ps |
| T790 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2921895445 |
|
|
May 28 03:47:26 PM PDT 24 |
May 28 04:42:49 PM PDT 24 |
25806825961 ps |
| T332 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3226582282 |
|
|
May 28 03:47:48 PM PDT 24 |
May 28 04:20:24 PM PDT 24 |
8729682930 ps |
| T791 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.584238926 |
|
|
May 28 04:14:00 PM PDT 24 |
May 28 04:43:51 PM PDT 24 |
9399280040 ps |
| T792 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2364615856 |
|
|
May 28 04:05:50 PM PDT 24 |
May 28 04:21:09 PM PDT 24 |
7177932200 ps |
| T115 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2438950228 |
|
|
May 28 03:54:14 PM PDT 24 |
May 28 03:57:18 PM PDT 24 |
3040615250 ps |
| T793 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.2359001855 |
|
|
May 28 04:23:06 PM PDT 24 |
May 28 04:34:40 PM PDT 24 |
5181617106 ps |
| T80 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.971900514 |
|
|
May 28 04:01:05 PM PDT 24 |
May 28 04:10:48 PM PDT 24 |
4018826400 ps |
| T794 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.151430591 |
|
|
May 28 04:10:08 PM PDT 24 |
May 28 04:13:40 PM PDT 24 |
2017977292 ps |
| T795 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.1000599579 |
|
|
May 28 04:01:47 PM PDT 24 |
May 28 04:04:42 PM PDT 24 |
2222150530 ps |
| T796 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.1530361309 |
|
|
May 28 03:42:11 PM PDT 24 |
May 28 03:52:49 PM PDT 24 |
4610320040 ps |
| T797 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2058498434 |
|
|
May 28 03:46:06 PM PDT 24 |
May 28 03:59:55 PM PDT 24 |
5319334560 ps |
| T488 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.170342558 |
|
|
May 28 04:27:35 PM PDT 24 |
May 28 04:35:20 PM PDT 24 |
5134372340 ps |
| T798 |
/workspace/coverage/default/2.rom_keymgr_functest.2951399456 |
|
|
May 28 04:16:28 PM PDT 24 |
May 28 04:26:45 PM PDT 24 |
5427882750 ps |
| T11 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1088440900 |
|
|
May 28 04:06:11 PM PDT 24 |
May 28 04:09:14 PM PDT 24 |
2442476392 ps |
| T445 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2811089405 |
|
|
May 28 04:20:30 PM PDT 24 |
May 28 04:26:59 PM PDT 24 |
4464703864 ps |
| T799 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1210882323 |
|
|
May 28 03:56:19 PM PDT 24 |
May 28 04:17:18 PM PDT 24 |
15827799451 ps |
| T236 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2441774555 |
|
|
May 28 04:06:39 PM PDT 24 |
May 28 04:20:27 PM PDT 24 |
5032308880 ps |
| T800 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2114625337 |
|
|
May 28 04:16:35 PM PDT 24 |
May 28 04:23:19 PM PDT 24 |
2730528720 ps |
| T801 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2259630506 |
|
|
May 28 04:26:43 PM PDT 24 |
May 28 04:31:32 PM PDT 24 |
3939731780 ps |
| T802 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1576014929 |
|
|
May 28 04:18:19 PM PDT 24 |
May 28 05:00:08 PM PDT 24 |
12775747579 ps |
| T803 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.653196138 |
|
|
May 28 04:16:20 PM PDT 24 |
May 28 04:26:36 PM PDT 24 |
4273186650 ps |
| T452 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1597180608 |
|
|
May 28 04:26:54 PM PDT 24 |
May 28 04:32:01 PM PDT 24 |
3663960368 ps |
| T108 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.3466161199 |
|
|
May 28 03:43:15 PM PDT 24 |
May 28 04:13:47 PM PDT 24 |
8041554720 ps |
| T804 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1614969844 |
|
|
May 28 04:10:39 PM PDT 24 |
May 28 04:14:56 PM PDT 24 |
3354607560 ps |
| T163 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3309782914 |
|
|
May 28 04:22:17 PM PDT 24 |
May 28 04:29:49 PM PDT 24 |
3654022028 ps |
| T417 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3110225340 |
|
|
May 28 04:25:04 PM PDT 24 |
May 28 04:31:03 PM PDT 24 |
2833832200 ps |
| T805 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3475381303 |
|
|
May 28 03:49:08 PM PDT 24 |
May 28 03:55:58 PM PDT 24 |
3525110680 ps |
| T806 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3636292263 |
|
|
May 28 04:15:12 PM PDT 24 |
May 28 04:23:34 PM PDT 24 |
4929707916 ps |
| T51 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.468914927 |
|
|
May 28 04:25:29 PM PDT 24 |
May 28 04:34:02 PM PDT 24 |
5958953970 ps |
| T807 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2600471723 |
|
|
May 28 04:17:48 PM PDT 24 |
May 28 04:23:28 PM PDT 24 |
6357727562 ps |
| T381 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1842041858 |
|
|
May 28 04:02:01 PM PDT 24 |
May 28 04:08:43 PM PDT 24 |
4573221904 ps |
| T808 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.3182880264 |
|
|
May 28 04:08:26 PM PDT 24 |
May 28 05:01:21 PM PDT 24 |
14487649087 ps |
| T809 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3298469025 |
|
|
May 28 03:46:24 PM PDT 24 |
May 28 04:17:28 PM PDT 24 |
8285822242 ps |
| T13 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.1594190800 |
|
|
May 28 03:56:09 PM PDT 24 |
May 28 04:00:48 PM PDT 24 |
3495068764 ps |
| T810 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3642832591 |
|
|
May 28 03:47:22 PM PDT 24 |
May 28 04:15:47 PM PDT 24 |
9474301807 ps |
| T811 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.630650354 |
|
|
May 28 04:10:30 PM PDT 24 |
May 28 04:44:54 PM PDT 24 |
11691933872 ps |
| T205 |
/workspace/coverage/default/0.chip_sw_flash_init.711338866 |
|
|
May 28 03:42:52 PM PDT 24 |
May 28 04:21:21 PM PDT 24 |
23684679952 ps |
| T812 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1368327535 |
|
|
May 28 04:06:24 PM PDT 24 |
May 28 04:19:01 PM PDT 24 |
3968905876 ps |
| T476 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3405281715 |
|
|
May 28 04:23:07 PM PDT 24 |
May 28 04:30:32 PM PDT 24 |
4041825700 ps |
| T140 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2002706213 |
|
|
May 28 04:03:41 PM PDT 24 |
May 28 04:39:44 PM PDT 24 |
10630162327 ps |
| T813 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2137349975 |
|
|
May 28 04:12:37 PM PDT 24 |
May 28 04:20:07 PM PDT 24 |
4414415640 ps |