Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3687378	1			T73	7254		T74	108		T75	1289
values[2]	756548	1			T73	2086		T74	63		T75	337
values[3]	113815	1			T73	705		T75	5		T144	1
values[4]	60900	1			T73	410		T79	3		T454	237
values[5]	40476	1			T73	245		T454	178		T525	47
values[6]	29850	1			T73	245		T454	134		T525	50
values[7]	23017	1			T73	223		T454	94		T525	29
values[8]	19682	1			T73	160		T454	72		T525	15
values[9]	17594	1			T73	124		T454	77		T525	6
values[10]	16258	1			T73	98		T454	87		T521	74
values[11]	14901	1			T73	65		T454	37		T521	77
values[12]	14098	1			T73	67		T454	46		T521	59
values[13]	13230	1			T73	74		T454	31		T521	50
values[14]	12386	1			T73	83		T454	15		T521	62
values[15]	12077	1			T73	106		T454	17		T521	64
values[16]	11487	1			T73	84		T454	34		T521	55
values[17]	11207	1			T73	73		T454	48		T521	56
values[18]	10643	1			T73	60		T454	28		T521	34
values[19]	10207	1			T73	43		T454	23		T521	21
values[20]	9639	1			T73	36		T454	15		T521	23
values[21]	8970	1			T73	29		T454	27		T521	24
values[22]	9062	1			T73	50		T454	11		T521	34
values[23]	8929	1			T73	39		T454	9		T521	17
values[24]	8743	1			T73	34		T454	12		T521	33
values[25]	8374	1			T73	32		T454	7		T521	35
values[26]	7925	1			T73	30		T454	12		T521	32
values[27]	7339	1			T73	29		T454	20		T521	32
values[28]	6965	1			T73	26		T454	18		T521	46
values[29]	6833	1			T73	15		T454	22		T521	37
values[30]	6404	1			T73	21		T454	27		T521	23
values[31]	5876	1			T73	9		T454	21		T521	22
values[32]	5330	1			T73	16		T454	33		T521	18
values[33]	5097	1			T73	44		T454	16		T521	26
values[34]	4659	1			T73	44		T454	10		T521	16
values[35]	4436	1			T73	15		T454	7		T521	6
values[36]	4272	1			T73	19		T454	7		T521	11
values[37]	3979	1			T73	18		T454	22		T521	12
values[38]	3821	1			T73	23		T454	28		T521	10
values[39]	3623	1			T73	28		T454	17		T521	12
values[40]	3542	1			T73	32		T454	14		T521	13
values[41]	3509	1			T73	25		T454	8		T521	10
values[42]	3378	1			T73	21		T454	7		T521	11
values[43]	3313	1			T73	26		T454	8		T521	9
values[44]	3289	1			T73	39		T454	7		T521	11
values[45]	3240	1			T73	29		T454	9		T521	10
values[46]	3167	1			T73	31		T454	10		T521	10
values[47]	3226	1			T73	27		T454	8		T521	9
values[48]	3113	1			T73	36		T454	14		T521	16
values[49]	3225	1			T73	21		T454	37		T521	7
values[50]	2988	1			T73	21		T454	12		T521	8
values[51]	2854	1			T73	26		T454	11		T521	7
values[52]	2846	1			T73	22		T454	11		T521	6
values[53]	2693	1			T73	16		T454	12		T521	12
values[54]	2681	1			T73	21		T454	14		T521	4
values[55]	2649	1			T73	24		T454	9		T521	5
values[56]	2601	1			T73	27		T454	7		T521	7
values[57]	2560	1			T73	20		T454	6		T521	9
values[58]	2549	1			T73	23		T454	9		T521	8
values[59]	2612	1			T73	22		T454	13		T521	11
values[60]	2597	1			T73	23		T454	10		T521	6
values[61]	2879	1			T73	11		T454	8		T521	10
values[62]	4849	1			T73	28		T454	35		T521	40
values[63]	18882	1			T73	49		T454	71		T521	148
values[64]	222302	1			T73	218		T454	263		T521	313

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4760951	1			T73	10962		T74	74		T75	1446
values[2]	796338	1			T73	2063		T74	26		T75	332
values[3]	79070	1			T73	362		T75	15		T144	1
values[4]	15193	1			T73	128		T79	39		T454	8
values[5]	6292	1			T73	53		T79	6		T454	14
values[6]	3994	1			T73	29		T79	1		T454	17
values[7]	3073	1			T73	14		T454	16		T525	20
values[8]	2555	1			T73	15		T454	12		T525	15
values[9]	2304	1			T73	13		T454	11		T525	3
values[10]	2127	1			T73	9		T454	17		T525	3
values[11]	1912	1			T73	3		T454	16		T525	1
values[12]	1637	1			T73	3		T454	15		T525	1
values[13]	1448	1			T73	4		T454	12		T525	4
values[14]	1291	1			T73	1		T454	6		T525	2
values[15]	1256	1			T454	12		T525	1		T521	15
values[16]	1193	1			T454	18		T521	17		T463	1
values[17]	1077	1			T454	11		T521	19		T463	2
values[18]	994	1			T454	6		T521	18		T463	4
values[19]	919	1			T454	4		T521	15		T463	2
values[20]	884	1			T454	2		T521	9		T463	6
values[21]	879	1			T454	6		T521	2		T463	3
values[22]	803	1			T454	3		T463	1		T780	7
values[23]	795	1			T454	3		T463	4		T780	3
values[24]	767	1			T454	2		T463	1		T780	6
values[25]	752	1			T454	6		T463	2		T780	12
values[26]	748	1			T454	7		T463	2		T780	6
values[27]	675	1			T454	4		T463	1		T780	9
values[28]	695	1			T454	4		T463	1		T780	5
values[29]	608	1			T454	7		T463	1		T780	4
values[30]	582	1			T454	7		T463	1		T780	4
values[31]	570	1			T454	7		T463	1		T780	4
values[32]	552	1			T454	2		T463	1		T780	8
values[33]	532	1			T454	3		T463	1		T780	5
values[34]	554	1			T454	6		T463	1		T780	4
values[35]	545	1			T454	7		T463	1		T780	4
values[36]	496	1			T454	3		T463	1		T780	3
values[37]	478	1			T454	2		T463	2		T780	3
values[38]	491	1			T454	2		T463	2		T780	11
values[39]	465	1			T454	2		T463	4		T780	8
values[40]	473	1			T454	6		T463	5		T780	3
values[41]	466	1			T454	11		T463	1		T780	4
values[42]	452	1			T454	15		T463	2		T780	5
values[43]	447	1			T454	15		T463	1		T780	6
values[44]	457	1			T454	3		T463	2		T780	12
values[45]	442	1			T454	8		T463	1		T780	8
values[46]	457	1			T454	6		T463	1		T780	9
values[47]	458	1			T454	14		T463	1		T780	7
values[48]	447	1			T454	16		T463	3		T780	5
values[49]	438	1			T454	12		T463	1		T780	4
values[50]	453	1			T454	11		T463	1		T780	5
values[51]	446	1			T454	4		T463	1		T780	5
values[52]	421	1			T454	1		T463	2		T780	6
values[53]	411	1			T454	2		T463	2		T780	3
values[54]	397	1			T454	2		T463	2		T780	5
values[55]	376	1			T463	1		T780	6		T685	1
values[56]	407	1			T463	1		T780	9		T685	1
values[57]	396	1			T463	2		T780	6		T685	1
values[58]	378	1			T463	1		T780	5		T685	1
values[59]	392	1			T463	1		T780	10		T685	1
values[60]	391	1			T463	1		T780	5		T685	2
values[61]	466	1			T463	2		T780	6		T685	1
values[62]	781	1			T463	2		T780	9		T685	2
values[63]	3470	1			T463	36		T780	34		T685	9
values[64]	26754	1			T463	145		T780	418		T685	104

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	604360	1			T73	180		T74	1		T75	16
values[2]	2532402	1			T73	3256		T74	62		T75	588
values[3]	1209124	1			T73	5679		T74	41		T75	1080
values[4]	167697	1			T73	663		T75	17		T144	3
values[5]	86022	1			T73	291		T79	3		T454	468
values[6]	55533	1			T73	243		T454	338		T534	103
values[7]	40531	1			T73	205		T454	172		T534	98
values[8]	31370	1			T73	208		T454	128		T534	61
values[9]	25964	1			T73	182		T454	105		T534	62
values[10]	21796	1			T73	136		T454	89		T534	70
values[11]	20108	1			T73	105		T454	47		T534	36
values[12]	18106	1			T73	92		T454	27		T534	48
values[13]	16451	1			T73	94		T454	52		T534	44
values[14]	15556	1			T73	87		T454	67		T534	19
values[15]	14387	1			T73	98		T454	71		T534	8
values[16]	14312	1			T73	89		T454	64		T534	8
values[17]	13244	1			T73	76		T454	43		T534	17
values[18]	12548	1			T73	58		T454	35		T534	8
values[19]	12349	1			T73	59		T454	40		T534	5
values[20]	11998	1			T73	47		T454	38		T534	5
values[21]	11275	1			T73	82		T454	50		T534	4
values[22]	10848	1			T73	59		T454	43		T534	7
values[23]	10444	1			T73	50		T454	65		T534	13
values[24]	10117	1			T73	45		T454	48		T534	5
values[25]	9742	1			T73	39		T454	41		T534	10
values[26]	8978	1			T73	32		T454	32		T534	10
values[27]	8585	1			T73	34		T454	27		T534	8
values[28]	8522	1			T73	36		T454	28		T534	7
values[29]	7970	1			T73	55		T454	26		T534	4
values[30]	7484	1			T73	46		T454	28		T534	14
values[31]	6887	1			T73	25		T454	28		T534	17
values[32]	6414	1			T73	24		T454	18		T534	5
values[33]	6013	1			T73	22		T454	18		T534	4
values[34]	5618	1			T73	22		T454	23		T534	4
values[35]	5031	1			T73	16		T454	18		T534	9
values[36]	4682	1			T73	16		T454	13		T534	4
values[37]	4503	1			T73	22		T454	23		T534	4
values[38]	4318	1			T73	23		T454	25		T534	6
values[39]	4059	1			T73	21		T454	18		T534	7
values[40]	4020	1			T73	28		T454	16		T534	11
values[41]	3928	1			T73	17		T454	21		T534	10
values[42]	3773	1			T73	21		T454	13		T534	8
values[43]	3688	1			T73	16		T454	12		T534	5
values[44]	3577	1			T73	20		T454	12		T534	8
values[45]	3616	1			T73	21		T454	28		T534	4
values[46]	3525	1			T73	22		T454	22		T534	7
values[47]	3390	1			T73	25		T454	17		T534	2
values[48]	3359	1			T73	18		T454	14		T534	3
values[49]	3321	1			T73	18		T454	31		T534	5
values[50]	3289	1			T73	17		T454	30		T534	4
values[51]	3318	1			T73	25		T454	12		T534	5
values[52]	3290	1			T73	23		T454	12		T534	4
values[53]	3118	1			T73	22		T454	15		T534	3
values[54]	3065	1			T73	20		T454	19		T534	5
values[55]	3004	1			T73	16		T454	13		T534	5
values[56]	2929	1			T73	11		T454	7		T534	5
values[57]	2923	1			T73	27		T454	7		T534	1
values[58]	2887	1			T73	31		T454	10		T534	4
values[59]	2966	1			T73	16		T454	14		T534	10
values[60]	2800	1			T73	8		T454	12		T534	6
values[61]	2947	1			T73	11		T454	12		T534	4
values[62]	4479	1			T73	14		T454	16		T534	16
values[63]	19065	1			T73	64		T454	22		T534	10
values[64]	210641	1			T73	398		T454	46		T534	32