Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2221723	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33421747

1

T4

10379

T5

5971

T6

44206

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	24674954	1			T4	5399		T5	970		T6	15777
values[0x0]	9152775	1			T4	4980		T5	5001		T6	28429
values[0x1]	1815741	1			T4	485		T5	71		T6	2022

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	552621	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

35090849

1

T4

10864

T5

6042

T6

46228

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16763196	1			T4	5432		T5	3022		T6	23116
valid_sources[0x01]	16761837	1			T4	5432		T5	3020		T6	23112
valid_sources[0x02]	33402	1			T8	4		T136	155		T137	861
valid_sources[0x03]	33711	1			T78	1		T136	170		T137	786
valid_sources[0x04]	34769	1			T78	4		T136	180		T137	791
valid_sources[0x05]	34371	1			T77	1		T9	4		T136	178
valid_sources[0x06]	33545	1			T77	2		T78	2		T136	160
valid_sources[0x07]	37006	1			T77	3		T78	1		T136	202
valid_sources[0x08]	34727	1			T77	2		T136	160		T137	777
valid_sources[0x09]	33948	1			T78	4		T9	2		T136	129
valid_sources[0x0a]	33444	1			T77	1		T136	163		T137	797
valid_sources[0x0b]	34279	1			T9	2		T136	157		T137	827
valid_sources[0x0c]	34347	1			T77	1		T136	194		T137	799
valid_sources[0x0d]	33474	1			T77	1		T9	3		T136	157
valid_sources[0x0e]	34384	1			T77	1		T8	1		T136	166
valid_sources[0x0f]	33413	1			T136	164		T137	815		T855	16
valid_sources[0x10]	34238	1			T77	1		T136	200		T137	817
valid_sources[0x11]	34596	1			T77	1		T136	136		T137	807
valid_sources[0x12]	33706	1			T77	1		T78	2		T9	1
valid_sources[0x13]	33996	1			T77	1		T78	3		T9	3
valid_sources[0x14]	33917	1			T136	164		T137	797		T855	26
valid_sources[0x15]	34843	1			T77	1		T136	214		T137	774
valid_sources[0x16]	34768	1			T77	1		T9	9		T136	173
valid_sources[0x17]	33994	1			T136	170		T137	783		T855	27
valid_sources[0x18]	34211	1			T77	2		T78	2		T136	160
valid_sources[0x19]	34333	1			T77	1		T8	11		T136	165
valid_sources[0x1a]	34614	1			T136	169		T137	754		T855	22
valid_sources[0x1b]	34106	1			T78	3		T136	198		T137	773
valid_sources[0x1c]	33671	1			T77	2		T136	173		T137	762
valid_sources[0x1d]	33959	1			T195	2		T136	184		T137	744
valid_sources[0x1e]	34318	1			T136	147		T137	780		T855	13
valid_sources[0x1f]	34108	1			T8	2		T136	156		T137	752
valid_sources[0x20]	34012	1			T136	159		T137	794		T855	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24063304

1

T4

5399

T5

970

T6

15777

values[0x0]

all_enables

biggest_size

9113913

1

T4

4980

T5

5001

T6

28429

values[0x1]

all_enables

biggest_size

244530

1

T77

15

T78

20

T8

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2904938	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

458604

1

T73

52

T74

25

T75

207

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1139330	1			T73	271		T74	59		T75	546
values[0x0]	1085229	1			T73	51		T74	60		T75	550
values[0x1]	1138983	1			T73	284		T74	52		T75	535

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2249580	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1113962

1

T73

225

T74

54

T75

527

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52864	1			T73	11		T74	1		T75	31
valid_sources[0x01]	52479	1			T73	7		T74	2		T75	29
valid_sources[0x02]	53022	1			T73	5		T74	4		T75	57
valid_sources[0x03]	52232	1			T73	11		T74	5		T75	27
valid_sources[0x04]	53726	1			T73	10		T74	2		T75	28
valid_sources[0x05]	53225	1			T73	12		T74	2		T75	10
valid_sources[0x06]	51818	1			T73	8		T74	2		T75	30
valid_sources[0x07]	52970	1			T73	12		T74	1		T75	16
valid_sources[0x08]	52576	1			T73	13		T74	4		T75	39
valid_sources[0x09]	53069	1			T73	7		T74	2		T75	18
valid_sources[0x0a]	52645	1			T73	3		T74	5		T75	22
valid_sources[0x0b]	52031	1			T73	10		T74	2		T75	35
valid_sources[0x0c]	54082	1			T73	9		T74	4		T75	3
valid_sources[0x0d]	52826	1			T73	8		T75	14		T144	1
valid_sources[0x0e]	52484	1			T73	10		T74	3		T75	19
valid_sources[0x0f]	52941	1			T73	8		T74	1		T75	15
valid_sources[0x10]	51607	1			T73	9		T74	4		T144	7
valid_sources[0x11]	51833	1			T73	17		T74	4		T75	23
valid_sources[0x12]	52174	1			T73	7		T75	39		T79	17
valid_sources[0x13]	52850	1			T73	5		T74	1		T75	24
valid_sources[0x14]	52538	1			T73	12		T74	5		T75	35
valid_sources[0x15]	51720	1			T73	8		T74	2		T75	35
valid_sources[0x16]	53576	1			T73	8		T74	3		T75	31
valid_sources[0x17]	53153	1			T73	11		T74	4		T75	41
valid_sources[0x18]	51929	1			T73	6		T74	3		T75	34
valid_sources[0x19]	52823	1			T73	13		T74	3		T75	46
valid_sources[0x1a]	52453	1			T73	9		T74	2		T75	12
valid_sources[0x1b]	51509	1			T73	10		T74	8		T75	11
valid_sources[0x1c]	53175	1			T73	12		T74	1		T75	26
valid_sources[0x1d]	53230	1			T73	7		T74	3		T75	11
valid_sources[0x1e]	52276	1			T73	11		T74	2		T75	6
valid_sources[0x1f]	51861	1			T73	12		T74	2		T75	32
valid_sources[0x20]	52373	1			T73	9		T74	4		T75	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48321

1

T73

22

T74

1

T75

21

values[0x0]

all_enables

biggest_size

362356

1

T73

22

T74

21

T75

169

values[0x1]

all_enables

biggest_size

47927

1

T73

8

T74

3

T75

17

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3093963	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

505134

1

T73

53

T74

12

T75

252

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1231069	1			T73	274		T74	31		T75	576
values[0x0]	1135781	1			T73	44		T74	37		T75	601
values[0x1]	1232247	1			T73	286		T74	32		T75	616

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2375757	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1223340

1

T73

224

T74

36

T75

614

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56808	1			T73	13		T74	3		T75	28
valid_sources[0x01]	56076	1			T73	8		T74	1		T75	17
valid_sources[0x02]	55849	1			T73	6		T75	21		T144	3
valid_sources[0x03]	56586	1			T73	6		T75	20		T79	39
valid_sources[0x04]	56615	1			T73	16		T74	2		T75	17
valid_sources[0x05]	56494	1			T73	8		T75	38		T144	2
valid_sources[0x06]	56065	1			T73	17		T74	1		T75	29
valid_sources[0x07]	56452	1			T73	9		T75	31		T144	8
valid_sources[0x08]	56859	1			T73	8		T74	1		T75	28
valid_sources[0x09]	56383	1			T73	7		T74	1		T75	32
valid_sources[0x0a]	56819	1			T73	7		T74	2		T75	39
valid_sources[0x0b]	56422	1			T73	14		T74	2		T75	34
valid_sources[0x0c]	56246	1			T73	7		T74	1		T75	32
valid_sources[0x0d]	56367	1			T73	8		T74	2		T75	40
valid_sources[0x0e]	57140	1			T73	15		T74	3		T75	21
valid_sources[0x0f]	56194	1			T73	12		T75	28		T79	29
valid_sources[0x10]	56406	1			T73	9		T74	1		T75	41
valid_sources[0x11]	56151	1			T73	6		T74	2		T75	23
valid_sources[0x12]	56210	1			T73	8		T74	2		T75	28
valid_sources[0x13]	56516	1			T73	5		T74	1		T75	23
valid_sources[0x14]	56011	1			T73	11		T74	2		T75	25
valid_sources[0x15]	55548	1			T73	12		T74	3		T75	25
valid_sources[0x16]	56600	1			T73	12		T74	1		T75	33
valid_sources[0x17]	57281	1			T73	10		T74	1		T75	41
valid_sources[0x18]	55692	1			T73	6		T74	2		T75	27
valid_sources[0x19]	56628	1			T73	15		T75	26		T144	5
valid_sources[0x1a]	56537	1			T73	12		T74	1		T75	28
valid_sources[0x1b]	55843	1			T73	1		T74	1		T75	29
valid_sources[0x1c]	57635	1			T73	11		T74	5		T75	22
valid_sources[0x1d]	56091	1			T73	10		T74	1		T75	26
valid_sources[0x1e]	56354	1			T73	7		T75	31		T144	1
valid_sources[0x1f]	55642	1			T73	3		T74	1		T75	29
valid_sources[0x20]	55351	1			T73	12		T74	1		T75	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53301

1

T73

18

T74

1

T75

22

values[0x0]

all_enables

biggest_size

399025

1

T73

16

T74

11

T75

202

values[0x1]

all_enables

biggest_size

52808

1

T73

19

T75

28

T144

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2929256	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

462669

1

T73

58

T74

14

T75

213

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1148847	1			T73	288		T74	32		T75	555
values[0x0]	1094448	1			T73	37		T74	32		T75	567
values[0x1]	1148630	1			T73	277		T74	40		T75	579

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2267579	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1124346

1

T73

227

T74

41

T75

539

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52884	1			T73	10		T75	26		T79	36
valid_sources[0x01]	53253	1			T73	7		T75	35		T144	1
valid_sources[0x02]	52340	1			T73	11		T74	3		T75	32
valid_sources[0x03]	53466	1			T73	10		T74	2		T75	22
valid_sources[0x04]	52759	1			T73	8		T75	30		T79	25
valid_sources[0x05]	54507	1			T73	10		T74	5		T75	32
valid_sources[0x06]	52429	1			T73	16		T75	28		T79	29
valid_sources[0x07]	52535	1			T73	13		T74	6		T75	26
valid_sources[0x08]	53928	1			T73	17		T75	28		T79	45
valid_sources[0x09]	53010	1			T73	12		T75	19		T144	6
valid_sources[0x0a]	53563	1			T73	8		T74	2		T75	21
valid_sources[0x0b]	53938	1			T73	9		T74	1		T75	24
valid_sources[0x0c]	53447	1			T73	6		T74	1		T75	29
valid_sources[0x0d]	52696	1			T73	5		T74	1		T75	31
valid_sources[0x0e]	53592	1			T73	11		T75	33		T79	33
valid_sources[0x0f]	53030	1			T73	6		T74	2		T75	32
valid_sources[0x10]	53153	1			T73	10		T74	5		T75	20
valid_sources[0x11]	53883	1			T73	10		T75	27		T79	33
valid_sources[0x12]	53156	1			T73	8		T75	26		T79	43
valid_sources[0x13]	52744	1			T73	16		T74	1		T75	32
valid_sources[0x14]	53825	1			T73	5		T74	4		T75	31
valid_sources[0x15]	52715	1			T73	13		T75	23		T79	37
valid_sources[0x16]	53021	1			T73	7		T74	3		T75	31
valid_sources[0x17]	53215	1			T73	7		T74	6		T75	35
valid_sources[0x18]	52510	1			T73	12		T74	2		T75	27
valid_sources[0x19]	52664	1			T73	5		T74	2		T75	22
valid_sources[0x1a]	53246	1			T73	10		T75	27		T79	34
valid_sources[0x1b]	52200	1			T73	13		T74	1		T75	26
valid_sources[0x1c]	52079	1			T73	9		T75	26		T144	2
valid_sources[0x1d]	52171	1			T73	5		T74	2		T75	27
valid_sources[0x1e]	53056	1			T73	6		T74	2		T75	22
valid_sources[0x1f]	52520	1			T73	7		T74	2		T75	24
valid_sources[0x20]	52091	1			T73	6		T75	35		T79	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48539

1

T73

19

T75

18

T144

2

values[0x0]

all_enables

biggest_size

365312

1

T73

20

T74

11

T75

171

values[0x1]

all_enables

biggest_size

48818

1

T73

19

T74

3

T75

24