Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.25			94.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	94.19			94.19
tb.dut.top_earlgrey.u_i2c1	94.22			94.22
tb.dut.top_earlgrey.u_i2c2	94.22			94.22

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.19			94.19

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.19			94.19

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22			94.22

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22			94.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22			94.22

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22			94.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	52	48	92.31
Total Bits	348	328	94.25
Total Bits 0->1	174	164	94.25
Total Bits 1->0	174	164	94.25

Ports	52	48	92.31
Port Bits	348	328	94.25
Port Bits 0->1	174	164	94.25
Port Bits 1->0	174	164	94.25

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T43	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T214,T307,T336	Yes	T214,T307,T336	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T214,T307,T336	Yes	T214,T307,T336	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T76,*T77	Yes	T20,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T77,T78,T8	Yes	T77,T78,T8	INPUT
tl_i.a_valid	Yes	Yes	T58,T151,T214	Yes	T58,T151,T214	INPUT
tl_o.a_ready	Yes	Yes	T58,T151,T214	Yes	T58,T151,T214	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T214,T307,T336	Yes	T214,T307,T336	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T151,T214,T307	Yes	T58,T151,T214	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T151,T214,T307	Yes	T58,T151,T214	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T9,*T11,*T73	Yes	T9,T11,T73	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T214,*T307,*T336	Yes	T214,T307,T336	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T58,T151,T214	Yes	T58,T151,T214	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T85,T58,T383	Yes	T85,T58,T383	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T383,T151,T150	Yes	T151,T150,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T151,T150,T81	Yes	T383,T151,T150	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T85,T58,T383	Yes	T85,T58,T383	OUTPUT
cio_scl_i	Yes	Yes	T214,T307,T336	Yes	T214,T307,T336	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T214,T207,T342	Yes	T214,T207,T342	OUTPUT
cio_sda_i	Yes	Yes	T214,T307,T336	Yes	T214,T307,T336	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T214,T307,T336	Yes	T214,T307,T336	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T214,T207,T325	Yes	T214,T207,T325	OUTPUT
intr_rx_threshold_o	Yes	Yes	T214,T207,T325	Yes	T214,T207,T325	OUTPUT
intr_acq_threshold_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_rx_overflow_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_controller_halt_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_scl_interference_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_sda_interference_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_sda_unstable_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_cmd_complete_o	Yes	Yes	T214,T307,T336	Yes	T214,T307,T336	OUTPUT
intr_tx_stretch_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_tx_threshold_o	Yes	Yes	T325,T326,T9	Yes	T325,T326,T9	OUTPUT
intr_acq_stretch_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_unexp_stop_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_host_timeout_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	52	48	92.31
Total Bits	344	324	94.19
Total Bits 0->1	172	162	94.19
Total Bits 1->0	172	162	94.19

Ports	52	48	92.31
Port Bits	344	324	94.19
Port Bits 0->1	172	162	94.19
Port Bits 1->0	172	162	94.19

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T43	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T336,T207,T325	Yes	T336,T207,T325	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T336,T207,T325	Yes	T336,T207,T325	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T76,*T77	Yes	T20,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T77,T78,T8	Yes	T77,T78,T8	INPUT
tl_i.a_valid	Yes	Yes	T58,T151,T324	Yes	T58,T151,T324	INPUT
tl_o.a_ready	Yes	Yes	T58,T151,T324	Yes	T58,T151,T324	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T336,T207,T325	Yes	T336,T207,T325	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T151,T324,T336	Yes	T58,T151,T324	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T151,T324,T336	Yes	T58,T151,T324	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T9,*T11,*T73	Yes	T9,T11,T73	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T336,*T207,*T325	Yes	T336,T207,T325	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T58,T151,T324	Yes	T58,T151,T324	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T85,T58,T151	Yes	T85,T58,T151	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T384,T205	Yes	T81,T205,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T205,T82	Yes	T81,T384,T205	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T85,T58,T151	Yes	T85,T58,T151	OUTPUT
cio_scl_i	Yes	Yes	T336,T207,T385	Yes	T336,T207,T385	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T207,T9,T385	Yes	T207,T9,T385	OUTPUT
cio_sda_i	Yes	Yes	T336,T207,T385	Yes	T336,T207,T385	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T336,T207,T9	Yes	T336,T207,T9	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T207,T325,T326	Yes	T207,T325,T326	OUTPUT
intr_rx_threshold_o	Yes	Yes	T207,T325,T326	Yes	T207,T325,T326	OUTPUT
intr_acq_threshold_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_rx_overflow_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_controller_halt_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_scl_interference_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_sda_interference_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_sda_unstable_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_cmd_complete_o	Yes	Yes	T336,T207,T325	Yes	T336,T207,T325	OUTPUT
intr_tx_stretch_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_tx_threshold_o	Yes	Yes	T325,T326,T9	Yes	T325,T326,T9	OUTPUT
intr_acq_stretch_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_unexp_stop_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_host_timeout_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	52	48	92.31
Total Bits	346	326	94.22
Total Bits 0->1	173	163	94.22
Total Bits 1->0	173	163	94.22

Ports	52	48	92.31
Port Bits	346	326	94.22
Port Bits 0->1	173	163	94.22
Port Bits 1->0	173	163	94.22

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T43	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T214,T325,T326	Yes	T214,T325,T326	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T214,T325,T326	Yes	T214,T325,T326	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T76,*T77	Yes	T20,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T77,T78,T8	Yes	T77,T78,T8	INPUT
tl_i.a_valid	Yes	Yes	T58,T151,T214	Yes	T58,T151,T214	INPUT
tl_o.a_ready	Yes	Yes	T58,T151,T214	Yes	T58,T151,T214	OUTPUT
tl_o.d_error	Yes	Yes	T73,T75,T79	Yes	T73,T75,T144	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T214,T325,T326	Yes	T214,T325,T326	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T151,T214,T324	Yes	T58,T151,T214	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T151,T214,T324	Yes	T58,T151,T214	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T75,T144	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T9,*T11,*T73	Yes	T9,T11,T73	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T75,T144	Yes	T73,T75,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T214,*T325,*T326	Yes	T214,T325,T326	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T58,T151,T214	Yes	T58,T151,T214	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T58,T383,T151	Yes	T58,T383,T151	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T383,T150,T81	Yes	T150,T81,T205	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T150,T81,T205	Yes	T383,T150,T81	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T58,T383,T151	Yes	T58,T383,T151	OUTPUT
cio_scl_i	Yes	Yes	T214,T342,T386	Yes	T214,T342,T386	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T214,T342,T9	Yes	T214,T342,T9	OUTPUT
cio_sda_i	Yes	Yes	T214,T342,T386	Yes	T214,T342,T386	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T214,T342,T386	Yes	T214,T342,T386	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T214,T325,T326	Yes	T214,T325,T326	OUTPUT
intr_rx_threshold_o	Yes	Yes	T214,T325,T326	Yes	T214,T325,T326	OUTPUT
intr_acq_threshold_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_rx_overflow_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_controller_halt_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_scl_interference_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_sda_interference_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_sda_unstable_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_cmd_complete_o	Yes	Yes	T214,T325,T326	Yes	T214,T325,T326	OUTPUT
intr_tx_stretch_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_tx_threshold_o	Yes	Yes	T325,T326,T11	Yes	T325,T326,T11	OUTPUT
intr_acq_stretch_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_unexp_stop_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_host_timeout_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	52	48	92.31
Total Bits	346	326	94.22
Total Bits 0->1	173	163	94.22
Total Bits 1->0	173	163	94.22

Ports	52	48	92.31
Port Bits	346	326	94.22
Port Bits 0->1	173	163	94.22
Port Bits 1->0	173	163	94.22

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T43	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T307,T325,T326	Yes	T307,T325,T326	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T307,T325,T326	Yes	T307,T325,T326	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T76,*T77	Yes	T20,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T77,T78,T8	Yes	T77,T78,T8	INPUT
tl_i.a_valid	Yes	Yes	T58,T151,T307	Yes	T58,T151,T307	INPUT
tl_o.a_ready	Yes	Yes	T58,T151,T307	Yes	T58,T151,T307	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T307,T325,T326	Yes	T307,T325,T326	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T151,T307,T324	Yes	T58,T151,T307	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T151,T307,T324	Yes	T58,T151,T307	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T9,*T11,*T73	Yes	T9,T11,T73	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T307,*T325,*T326	Yes	T307,T325,T326	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T58,T151,T307	Yes	T58,T151,T307	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T58,T151,T150	Yes	T58,T151,T150	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T151,T150,T81	Yes	T151,T150,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T151,T150,T81	Yes	T151,T150,T81	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T58,T151,T150	Yes	T58,T151,T150	OUTPUT
cio_scl_i	Yes	Yes	T307,T343,T344	Yes	T307,T343,T344	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T343,T344,T337	Yes	T343,T344,T337	OUTPUT
cio_sda_i	Yes	Yes	T307,T343,T344	Yes	T307,T343,T344	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T307,T343,T344	Yes	T307,T343,T344	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T325,T326,T343	Yes	T325,T326,T343	OUTPUT
intr_rx_threshold_o	Yes	Yes	T325,T326,T343	Yes	T325,T326,T343	OUTPUT
intr_acq_threshold_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_rx_overflow_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_controller_halt_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_scl_interference_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_sda_interference_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_sda_unstable_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_cmd_complete_o	Yes	Yes	T307,T325,T326	Yes	T307,T325,T326	OUTPUT
intr_tx_stretch_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_tx_threshold_o	Yes	Yes	T325,T326,T9	Yes	T325,T326,T9	OUTPUT
intr_acq_stretch_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_unexp_stop_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT
intr_host_timeout_o	Yes	Yes	T325,T326,T331	Yes	T325,T326,T331	OUTPUT

*Tests covering at least one bit in the range