Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	485985293	51926317	0	0
DepthKnown_A	485985293	485881107	0	0
RvalidKnown_A	485985293	485881107	0	0
WreadyKnown_A	485985293	485881107	0	0
gen_passthru_fifo.paramCheckPass	984	984	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	51926317	0	0
T4	154066	15850	0	0
T5	165953	12685	0	0
T6	105247	114315	0	0
T17	607958	71857	0	0
T31	115061	43088	0	0
T43	184813	15699	0	0
T50	120373	12666	0	0
T61	287615	36123	0	0
T84	149075	24864	0	0
T85	152238	25624	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	485881107	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	485881107	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	485881107	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	984	984	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T50	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	485985293	41206364	0	0
DepthKnown_A	485985293	485881107	0	0
RvalidKnown_A	485985293	485881107	0	0
WreadyKnown_A	485985293	485881107	0	0
gen_passthru_fifo.paramCheckPass	984	984	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	41206364	0	0
T4	154066	12151	0	0
T5	165953	8412	0	0
T6	105247	82521	0	0
T17	607958	56485	0	0
T31	115061	34454	0	0
T43	184813	11847	0	0
T50	120373	8646	0	0
T61	287615	27031	0	0
T84	149075	17198	0	0
T85	152238	17958	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	485881107	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	485881107	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	485881107	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	984	984	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T50	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	485985293	39272595	0	0
DepthKnown_A	485985293	485881107	0	0
RvalidKnown_A	485985293	485881107	0	0
WreadyKnown_A	485985293	485881107	0	0
gen_passthru_fifo.paramCheckPass	984	984	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	39272595	0	0
T4	154066	11043	0	0
T5	165953	6284	0	0
T6	105247	47727	0	0
T17	607958	26773	0	0
T31	115061	25971	0	0
T43	184813	9212	0	0
T50	120373	9791	0	0
T61	287615	20129	0	0
T84	149075	8437	0	0
T85	152238	8984	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	485881107	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	485881107	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	485881107	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	984	984	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T50	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	485985293	33510591	0	0
DepthKnown_A	485985293	485881107	0	0
RvalidKnown_A	485985293	485881107	0	0
WreadyKnown_A	485985293	485881107	0	0
gen_passthru_fifo.paramCheckPass	984	984	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	33510591	0	0
T4	154066	10864	0	0
T5	165953	6042	0	0
T6	105247	46228	0	0
T17	607958	25995	0	0
T31	115061	25410	0	0
T43	184813	8972	0	0
T50	120373	9498	0	0
T61	287615	19746	0	0
T84	149075	8159	0	0
T85	152238	8706	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	485881107	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	485881107	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	485881107	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	984	984	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T50	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	553101789	89732	0	0
DepthKnown_A	553101789	552985509	0	0
RvalidKnown_A	553101789	552985509	0	0
WreadyKnown_A	553101789	552985509	0	0
gen_passthru_fifo.paramCheckPass	2874	2874	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	89732	0	0
T4	154066	15	0	0
T5	165953	30	0	0
T6	105247	218	0	0
T17	607958	116	0	0
T31	115061	63	0	0
T43	184813	28	0	0
T50	120373	94	0	0
T61	287615	151	0	0
T84	149075	26	0	0
T85	152238	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2874	2874	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T50	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	553101789	93745	0	0
DepthKnown_A	553101789	552985509	0	0
RvalidKnown_A	553101789	552985509	0	0
WreadyKnown_A	553101789	552985509	0	0
gen_passthru_fifo.paramCheckPass	2874	2874	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	93745	0	0
T4	154066	15	0	0
T5	165953	30	0	0
T6	105247	218	0	0
T17	607958	116	0	0
T31	115061	63	0	0
T43	184813	28	0	0
T50	120373	94	0	0
T61	287615	151	0	0
T84	149075	26	0	0
T85	152238	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2874	2874	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T50	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	553101789	50131	0	0
DepthKnown_A	553101789	552985509	0	0
RvalidKnown_A	553101789	552985509	0	0
WreadyKnown_A	553101789	552985509	0	0
gen_passthru_fifo.paramCheckPass	2874	2874	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	50131	0	0
T4	154066	12	0	0
T5	165953	28	0	0
T6	105247	191	0	0
T17	607958	101	0	0
T31	115061	59	0	0
T43	184813	26	0	0
T50	120373	93	0	0
T61	287615	95	0	0
T84	149075	23	0	0
T85	152238	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2874	2874	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T50	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	553101789	50131	0	0
DepthKnown_A	553101789	552985509	0	0
RvalidKnown_A	553101789	552985509	0	0
WreadyKnown_A	553101789	552985509	0	0
gen_passthru_fifo.paramCheckPass	2874	2874	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	50131	0	0
T4	154066	12	0	0
T5	165953	28	0	0
T6	105247	191	0	0
T17	607958	101	0	0
T31	115061	59	0	0
T43	184813	26	0	0
T50	120373	93	0	0
T61	287615	95	0	0
T84	149075	23	0	0
T85	152238	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2874	2874	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T50	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	553101789	39601	0	0
DepthKnown_A	553101789	552985509	0	0
RvalidKnown_A	553101789	552985509	0	0
WreadyKnown_A	553101789	552985509	0	0
gen_passthru_fifo.paramCheckPass	2874	2874	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	39601	0	0
T4	154066	3	0	0
T5	165953	2	0	0
T6	105247	27	0	0
T17	607958	15	0	0
T31	115061	4	0	0
T43	184813	2	0	0
T50	120373	1	0	0
T61	287615	56	0	0
T84	149075	3	0	0
T85	152238	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2874	2874	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T50	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	553101789	43614	0	0
DepthKnown_A	553101789	552985509	0	0
RvalidKnown_A	553101789	552985509	0	0
WreadyKnown_A	553101789	552985509	0	0
gen_passthru_fifo.paramCheckPass	2874	2874	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	43614	0	0
T4	154066	3	0	0
T5	165953	2	0	0
T6	105247	27	0	0
T17	607958	15	0	0
T31	115061	4	0	0
T43	184813	2	0	0
T50	120373	1	0	0
T61	287615	56	0	0
T84	149075	3	0	0
T85	152238	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	553101789	552985509	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2874	2874	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T50	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0