Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T43	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T19,T94	Yes	T18,T19,T94	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T18,T19,T94	Yes	T18,T19,T94	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T76,*T77	Yes	T20,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T77,T78,T8	Yes	T77,T78,T8	INPUT
tl_i.a_valid	Yes	Yes	T18,T58,T19	Yes	T18,T58,T19	INPUT
tl_o.a_ready	Yes	Yes	T18,T58,T19	Yes	T18,T58,T19	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T19,T94	Yes	T18,T19,T94	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T18,T19,T94	Yes	T18,T58,T19	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T19,T94	Yes	T18,T58,T19	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T8,*T73,*T75	Yes	T8,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T19,*T94	Yes	T18,T19,T94	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T18,T58,T19	Yes	T18,T58,T19	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T61,T58,T670	Yes	T61,T58,T670	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T150,T81,T82	Yes	T150,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T150,T81,T82	Yes	T150,T81,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T61,T58,T670	Yes	T61,T58,T670	OUTPUT
cio_rx_i	Yes	Yes	T5,T6,T43	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T18,T19,T94	Yes	T18,T19,T94	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T94,T203,T218	Yes	T94,T203,T218	OUTPUT
intr_rx_watermark_o	Yes	Yes	T94,T203,T218	Yes	T94,T203,T218	OUTPUT
intr_tx_empty_o	Yes	Yes	T94,T203,T218	Yes	T94,T203,T218	OUTPUT
intr_rx_overflow_o	Yes	Yes	T94,T203,T218	Yes	T94,T203,T218	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT
intr_rx_break_err_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT
intr_rx_timeout_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T43	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T19,T94	Yes	T18,T19,T94	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T18,T19,T94	Yes	T18,T19,T94	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T76,*T77	Yes	T20,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T77,T78,T8	Yes	T77,T78,T8	INPUT
tl_i.a_valid	Yes	Yes	T18,T58,T19	Yes	T18,T58,T19	INPUT
tl_o.a_ready	Yes	Yes	T18,T58,T19	Yes	T18,T58,T19	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T75,T144	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T19,T94	Yes	T18,T19,T94	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T18,T19,T94	Yes	T18,T58,T19	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T19,T94	Yes	T18,T58,T19	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T8,*T73,*T75	Yes	T8,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T75,T144	Yes	T73,T75,T144	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T19,*T94	Yes	T18,T19,T94	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T18,T58,T19	Yes	T18,T58,T19	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T58,T670,T348	Yes	T58,T670,T348	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T58,T670,T348	Yes	T58,T670,T348	OUTPUT
cio_rx_i	Yes	Yes	T5,T6,T43	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T18,T19,T94	Yes	T18,T19,T94	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T94,T218,T110	Yes	T94,T218,T110	OUTPUT
intr_rx_watermark_o	Yes	Yes	T94,T218,T110	Yes	T94,T218,T110	OUTPUT
intr_tx_empty_o	Yes	Yes	T94,T218,T110	Yes	T94,T218,T110	OUTPUT
intr_rx_overflow_o	Yes	Yes	T94,T218,T110	Yes	T94,T218,T110	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT
intr_rx_break_err_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT
intr_rx_timeout_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T43	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T208,T209,T327	Yes	T208,T209,T327	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T208,T209,T327	Yes	T208,T209,T327	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T76,*T77	Yes	T20,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T77,T78,T8	Yes	T77,T78,T8	INPUT
tl_i.a_valid	Yes	Yes	T58,T151,T208	Yes	T58,T151,T208	INPUT
tl_o.a_ready	Yes	Yes	T58,T151,T208	Yes	T58,T151,T208	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T208,T209,T327	Yes	T208,T209,T327	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T151,T208,T324	Yes	T58,T151,T208	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T151,T208,T324	Yes	T58,T151,T208	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T75,T144	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T8,*T73,*T75	Yes	T8,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T208,*T209,*T327	Yes	T208,T209,T327	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T58,T151,T208	Yes	T58,T151,T208	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T61,T58,T151	Yes	T61,T58,T151	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T149	Yes	T81,T82,T149	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T149	Yes	T81,T82,T149	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T61,T58,T151	Yes	T61,T58,T151	OUTPUT
cio_rx_i	Yes	Yes	T208,T44,T209	Yes	T208,T44,T209	INPUT
cio_tx_o	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T208,T209,T327	Yes	T208,T209,T327	OUTPUT
intr_rx_watermark_o	Yes	Yes	T208,T209,T327	Yes	T208,T209,T327	OUTPUT
intr_tx_empty_o	Yes	Yes	T208,T209,T327	Yes	T208,T209,T327	OUTPUT
intr_rx_overflow_o	Yes	Yes	T208,T209,T327	Yes	T208,T209,T327	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT
intr_rx_break_err_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT
intr_rx_timeout_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T43	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T203,T109,T335	Yes	T203,T109,T335	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T203,T109,T335	Yes	T203,T109,T335	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T76,*T77	Yes	T20,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T77,T78,T8	Yes	T77,T78,T8	INPUT
tl_i.a_valid	Yes	Yes	T58,T203,T109	Yes	T58,T203,T109	INPUT
tl_o.a_ready	Yes	Yes	T58,T203,T109	Yes	T58,T203,T109	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T203,T109,T335	Yes	T203,T109,T335	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T203,T109,T151	Yes	T58,T203,T109	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T203,T109,T151	Yes	T58,T203,T109	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T8,*T73,*T75	Yes	T8,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T203,*T109,*T335	Yes	T203,T109,T335	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T58,T203,T109	Yes	T58,T203,T109	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T58,T151,T324	Yes	T58,T151,T324	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T58,T151,T324	Yes	T58,T151,T324	OUTPUT
cio_rx_i	Yes	Yes	T203,T109,T335	Yes	T203,T109,T335	INPUT
cio_tx_o	Yes	Yes	T203,T109,T335	Yes	T203,T109,T335	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T203,T109,T335	Yes	T203,T109,T335	OUTPUT
intr_rx_watermark_o	Yes	Yes	T203,T109,T335	Yes	T203,T109,T335	OUTPUT
intr_tx_empty_o	Yes	Yes	T203,T109,T335	Yes	T203,T109,T335	OUTPUT
intr_rx_overflow_o	Yes	Yes	T203,T109,T335	Yes	T203,T109,T335	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT
intr_rx_break_err_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT
intr_rx_timeout_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T43	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T76,*T77	Yes	T20,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T77,T78,T8	Yes	T77,T78,T8	INPUT
tl_i.a_valid	Yes	Yes	T58,T151,T328	Yes	T58,T151,T328	INPUT
tl_o.a_ready	Yes	Yes	T58,T151,T328	Yes	T58,T151,T328	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T151,T328,T329	Yes	T58,T151,T328	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T151,T328,T329	Yes	T58,T151,T328	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T75,T79	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T8,*T73,*T75	Yes	T8,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T75,T144	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T328,*T329,*T330	Yes	T328,T329,T330	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T58,T151,T328	Yes	T58,T151,T328	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T58,T151,T150	Yes	T58,T151,T150	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T150,T81,T82	Yes	T150,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T150,T81,T82	Yes	T150,T81,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T58,T151,T150	Yes	T58,T151,T150	OUTPUT
cio_rx_i	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	INPUT
cio_tx_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_watermark_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_tx_empty_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_overflow_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT
intr_rx_break_err_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT
intr_rx_timeout_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T327,T338,T345	Yes	T327,T338,T345	OUTPUT

*Tests covering at least one bit in the range