Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_por_aon_n_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T31,T21,T24
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T21,T24
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T31,T21,T24

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	26910	26540	0	0
selKnown1	35900	34638	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	26910	26540	0	0
T20	3	2	0	0
T21	1	0	0	0
T22	1	0	0	0
T23	1	0	0	0
T24	2552	2550	0	0
T25	4961	4959	0	0
T26	2816	2814	0	0
T27	33	32	0	0
T40	16	19	0	0
T41	0	15	0	0
T42	0	6	0	0
T45	159	157	0	0
T46	122	0	0	0
T55	3	2	0	0
T56	3	2	0	0
T57	1	0	0	0
T62	0	34	0	0
T65	0	1	0	0
T108	4	3	0	0
T111	1	0	0	0
T159	3	2	0	0
T167	6	5	0	0
T168	0	5	0	0
T184	3151	3149	0	0
T185	5572	5570	0	0
T186	3065	3063	0	0
T187	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	35900	34638	0	0
T5	2	1	0	0
T6	9	8	0	0
T17	5	4	0	0
T18	0	1	0	0
T31	3	2	0	0
T40	32	30	0	0
T41	45	43	0	0
T42	20	18	0	0
T43	2	1	0	0
T44	545	544	0	0
T50	1	0	0	0
T61	2	1	0	0
T80	0	1	0	0
T84	1	0	0	0
T85	1	0	0	0
T103	0	1	0	0
T181	0	2	0	0
T187	24	22	0	0
T188	34	32	0	0
T189	6	4	0	0
T190	13	26	0	0
T191	5	10	0	0
T192	23	37	0	0
T193	11	10	0	0
T194	1	0	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	689	672	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	689	672	0	0
T40	16	15	0	0
T41	25	24	0	0
T42	10	9	0	0
T44	545	544	0	0
T184	1	0	0	0
T185	1	0	0	0
T186	1	0	0	0
T187	14	13	0	0
T188	21	20	0	0
T189	2	1	0	0
T190	0	14	0	0
T191	0	6	0	0
T192	0	15	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T44,T40
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	127	115	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	127	115	0	0
T40	16	15	0	0
T41	20	19	0	0
T42	10	9	0	0
T187	10	9	0	0
T188	13	12	0	0
T189	4	3	0	0
T190	13	12	0	0
T191	5	4	0	0
T192	23	22	0	0
T193	11	10	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T44,T22
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	132	117	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	132	117	0	0
T22	1	0	0	0
T40	20	19	0	0
T41	14	13	0	0
T42	8	7	0	0
T44	2	1	0	0
T45	1	0	0	0
T46	1	0	0	0
T187	16	15	0	0
T188	13	12	0	0
T189	7	6	0	0
T190	0	10	0	0
T191	0	14	0	0
T192	0	9	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T44,T22
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	105	91	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	105	91	0	0
T40	11	10	0	0
T41	8	7	0	0
T42	7	6	0	0
T187	10	9	0	0
T188	13	12	0	0
T189	5	4	0	0
T190	15	14	0	0
T191	9	8	0	0
T192	11	10	0	0
T193	12	11	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T40
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	174	162	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	174	162	0	0
T40	17	16	0	0
T41	26	25	0	0
T42	18	17	0	0
T187	15	14	0	0
T188	18	17	0	0
T189	8	7	0	0
T190	17	16	0	0
T191	18	17	0	0
T192	21	20	0	0
T193	14	13	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	128	115	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	128	115	0	0
T40	11	10	0	0
T41	18	17	0	0
T42	12	11	0	0
T187	12	11	0	0
T188	14	13	0	0
T189	4	3	0	0
T190	13	12	0	0
T191	16	15	0	0
T192	15	14	0	0
T193	10	9	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T57,T21
0	1	Covered	T20,T57,T21
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T20,T57,T21
1	1	Covered	T20,T57,T21

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	889	767	0	0
selKnown1	1715	741	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	889	767	0	0
T20	3	2	0	0
T21	1	0	0	0
T27	33	32	0	0
T55	3	2	0	0
T56	3	2	0	0
T57	1	0	0	0
T62	0	34	0	0
T65	0	1	0	0
T108	4	3	0	0
T111	1	0	0	0
T159	3	2	0	0
T167	6	5	0	0
T168	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1715	741	0	0
T5	2	1	0	0
T6	9	8	0	0
T17	5	4	0	0
T18	0	1	0	0
T31	3	2	0	0
T43	2	1	0	0
T50	1	0	0	0
T61	2	1	0	0
T80	0	1	0	0
T84	1	0	0	0
T85	1	0	0	0
T103	0	1	0	0
T181	0	2	0	0
T194	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T25,T26
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T44,T22,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T24,T25,T26

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22280	22262	0	0
selKnown1	270	257	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	22280	22262	0	0
T24	2478	2477	0	0
T25	4948	4947	0	0
T26	2741	2740	0	0
T40	16	15	0	0
T41	13	12	0	0
T45	158	157	0	0
T46	121	120	0	0
T184	3073	3072	0	0
T185	5559	5558	0	0
T186	3046	3045	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	270	257	0	0
T22	1	0	0	0
T23	1	0	0	0
T40	13	12	0	0
T41	13	12	0	0
T42	15	14	0	0
T44	132	131	0	0
T187	20	19	0	0
T188	19	18	0	0
T189	5	4	0	0
T190	8	7	0	0
T191	0	10	0	0
T192	0	17	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T25,T26
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T44,T22
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T24,T25,T26

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	335	315	0	0
selKnown1	134	120	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	335	315	0	0
T22	1	0	0	0
T23	1	0	0	0
T24	74	73	0	0
T25	13	12	0	0
T26	75	74	0	0
T40	0	4	0	0
T41	0	3	0	0
T42	0	6	0	0
T45	1	0	0	0
T46	1	0	0	0
T184	78	77	0	0
T185	13	12	0	0
T186	19	18	0	0
T187	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	134	120	0	0
T40	9	8	0	0
T41	12	11	0	0
T42	15	14	0	0
T187	17	16	0	0
T188	23	22	0	0
T189	5	4	0	0
T190	7	6	0	0
T191	12	11	0	0
T192	17	16	0	0
T193	13	12	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T44,T77
0	1	Covered	T44,T22,T23
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T44,T77
1	1	Covered	T44,T22,T23

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	798	777	0	0
selKnown1	54	33	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	798	777	0	0
T8	1	0	0	0
T9	1	0	0	0
T11	1	0	0	0
T22	1	0	0	0
T23	1	0	0	0
T40	0	21	0	0
T41	0	33	0	0
T42	0	19	0	0
T44	546	545	0	0
T45	1	0	0	0
T77	1	0	0	0
T78	1	0	0	0
T187	0	22	0	0
T188	0	20	0	0
T189	0	16	0	0
T190	0	38	0	0
T191	0	19	0	0
T192	0	27	0	0
T195	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	54	33	0	0
T21	2	1	0	0
T22	2	1	0	0
T23	2	1	0	0
T28	1	0	0	0
T34	1	0	0	0
T35	1	0	0	0
T36	1	0	0	0
T40	0	3	0	0
T41	0	3	0	0
T42	0	3	0	0
T70	1	0	0	0
T71	1	0	0	0
T139	1	0	0	0
T187	0	3	0	0
T188	0	3	0	0
T189	0	3	0	0
T190	0	3	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T44,T77
0	1	Covered	T44,T22,T23
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T44,T77
1	1	Covered	T44,T22,T23

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	802	781	0	0
selKnown1	54	33	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	802	781	0	0
T8	1	0	0	0
T9	1	0	0	0
T11	1	0	0	0
T22	1	0	0	0
T23	1	0	0	0
T40	0	23	0	0
T41	0	31	0	0
T42	0	21	0	0
T44	546	545	0	0
T45	1	0	0	0
T77	1	0	0	0
T78	1	0	0	0
T187	0	23	0	0
T188	0	20	0	0
T189	0	15	0	0
T190	0	40	0	0
T191	0	19	0	0
T192	0	27	0	0
T195	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	54	33	0	0
T21	2	1	0	0
T22	2	1	0	0
T23	2	1	0	0
T28	1	0	0	0
T34	1	0	0	0
T35	1	0	0	0
T36	1	0	0	0
T40	0	3	0	0
T41	0	3	0	0
T42	0	3	0	0
T70	1	0	0	0
T71	1	0	0	0
T139	1	0	0	0
T187	0	3	0	0
T188	0	3	0	0
T189	0	3	0	0
T190	0	3	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T44,T77,T78
0	1	Covered	T21,T24,T25
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T44,T77,T78
1	1	Covered	T21,T24,T25

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	220	193	0	0
selKnown1	24	3	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	220	193	0	0
T8	1	0	0	0
T9	1	0	0	0
T11	1	0	0	0
T22	1	0	0	0
T40	0	19	0	0
T41	0	19	0	0
T42	0	14	0	0
T44	2	1	0	0
T45	1	0	0	0
T77	1	0	0	0
T78	1	0	0	0
T184	1	0	0	0
T185	1	0	0	0
T187	0	22	0	0
T188	0	8	0	0
T189	0	31	0	0
T190	0	15	0	0
T191	0	25	0	0
T192	0	24	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	24	3	0	0
T21	2	1	0	0
T22	2	1	0	0
T23	2	1	0	0
T28	1	0	0	0
T34	1	0	0	0
T35	1	0	0	0
T36	1	0	0	0
T70	1	0	0	0
T71	1	0	0	0
T139	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T44,T77,T78
0	1	Covered	T21,T24,T25
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T44,T77,T78
1	1	Covered	T21,T24,T25

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	224	197	0	0
selKnown1	24	3	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	224	197	0	0
T8	1	0	0	0
T9	1	0	0	0
T11	1	0	0	0
T22	1	0	0	0
T40	0	20	0	0
T41	0	19	0	0
T42	0	14	0	0
T44	2	1	0	0
T45	1	0	0	0
T77	1	0	0	0
T78	1	0	0	0
T184	1	0	0	0
T185	1	0	0	0
T187	0	22	0	0
T188	0	7	0	0
T189	0	31	0	0
T190	0	16	0	0
T191	0	25	0	0
T192	0	25	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	24	3	0	0
T21	2	1	0	0
T22	2	1	0	0
T23	2	1	0	0
T28	1	0	0	0
T34	1	0	0	0
T35	1	0	0	0
T36	1	0	0	0
T70	1	0	0	0
T71	1	0	0	0
T139	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T77,T78
0	1	Covered	T22,T23,T40
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T77,T78
1	1	Covered	T22,T23,T40

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	207	189	0	0
selKnown1	24	3	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	207	189	0	0
T40	18	17	0	0
T41	18	17	0	0
T42	22	21	0	0
T187	25	24	0	0
T188	19	18	0	0
T189	10	9	0	0
T190	25	24	0	0
T191	26	25	0	0
T192	23	22	0	0
T193	13	12	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	24	3	0	0
T21	2	1	0	0
T22	2	1	0	0
T23	2	1	0	0
T28	1	0	0	0
T34	1	0	0	0
T35	1	0	0	0
T36	1	0	0	0
T70	1	0	0	0
T71	1	0	0	0
T139	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T77,T78
0	1	Covered	T22,T23,T40
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T77,T78
1	1	Covered	T22,T23,T40

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	205	187	0	0
selKnown1	24	3	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	205	187	0	0
T40	17	16	0	0
T41	19	18	0	0
T42	22	21	0	0
T187	25	24	0	0
T188	19	18	0	0
T189	10	9	0	0
T190	25	24	0	0
T191	25	24	0	0
T192	22	21	0	0
T193	13	12	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	24	3	0	0
T21	2	1	0	0
T22	2	1	0	0
T23	2	1	0	0
T28	1	0	0	0
T34	1	0	0	0
T35	1	0	0	0
T36	1	0	0	0
T70	1	0	0	0
T71	1	0	0	0
T139	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T31,T21,T32
0	1	Covered	T31,T24,T32
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T24,T25
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T31,T21,T32
1	1	Covered	T31,T24,T32

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	472	433	0	0
selKnown1	16113	16087	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	472	433	0	0
T24	1	0	0	0
T25	1	0	0	0
T26	1	0	0	0
T31	2	1	0	0
T32	2	1	0	0
T33	1	0	0	0
T44	127	126	0	0
T77	1	0	0	0
T184	1	0	0	0
T196	39	38	0	0
T197	0	1	0	0
T198	0	37	0	0
T199	0	1	0	0
T200	0	31	0	0
T201	0	1	0	0
T202	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	16113	16087	0	0
T8	1	0	0	0
T9	1	0	0	0
T24	1576	1575	0	0
T25	4924	4923	0	0
T26	1726	1725	0	0
T40	0	15	0	0
T41	0	15	0	0
T44	1	0	0	0
T45	0	151	0	0
T46	0	114	0	0
T77	1	0	0	0
T78	1	0	0	0
T184	1912	1911	0	0
T185	5514	5513	0	0
T186	0	55	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T31,T21,T32
0	1	Covered	T31,T24,T32
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T24,T25
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T31,T21,T32
1	1	Covered	T31,T24,T32

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	478	439	0	0
selKnown1	16109	16083	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	478	439	0	0
T24	1	0	0	0
T25	1	0	0	0
T26	1	0	0	0
T31	2	1	0	0
T32	2	1	0	0
T33	1	0	0	0
T44	127	126	0	0
T77	1	0	0	0
T184	1	0	0	0
T196	39	38	0	0
T197	0	1	0	0
T198	0	37	0	0
T199	0	1	0	0
T200	0	31	0	0
T201	0	1	0	0
T202	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	16109	16083	0	0
T8	1	0	0	0
T9	1	0	0	0
T24	1576	1575	0	0
T25	4924	4923	0	0
T26	1726	1725	0	0
T40	0	15	0	0
T41	0	14	0	0
T44	1	0	0	0
T45	0	151	0	0
T46	0	114	0	0
T77	1	0	0	0
T78	1	0	0	0
T184	1912	1911	0	0
T185	5514	5513	0	0
T186	0	55	0	0