Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T175,T176,T177
0	1	Covered	T175,T176,T177
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T175,T176,T177
1	Covered	T175,T176,T177

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T175,T176,T177
1	Covered	T175,T176,T177

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T175,T176,T177
1	1	Covered	T175,T176,T177

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T175,T176,T177
1	0	Covered	T175,T176,T177
1	1	Covered	T175,T176,T177

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T175,T176,T177

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T175,T176,T177
0	Covered	T175,T176,T177

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T175,T176,T177
0	Covered	T175,T176,T177

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	971970586	951895072	0	0
CheckNGreaterZero_A	1968	1968	0	0
GntImpliesReady_A	971970586	8454	0	0
GntImpliesValid_A	971970586	8454	0	0
GrantKnown_A	971970586	951895072	0	0
IdxKnown_A	971970586	951895072	0	0
IndexIsCorrect_A	971970586	8454	0	0
NoReadyValidNoGrant_A	971970586	0	0	0
Priority_A	971970586	8454	0	0
ReadyAndValidImplyGrant_A	971970586	8454	0	0
ReqAndReadyImplyGrant_A	971970586	8454	0	0
ReqImpliesValid_A	971970586	8454	0	0
ValidKnown_A	971970586	951895072	0	0
gen_data_port_assertion.DataFlow_A	971970586	8454	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971970586	951895072	0	0
T4	308132	308016	0	0
T5	331906	331672	0	0
T6	210494	210374	0	0
T17	1215916	1215362	0	0
T31	230122	230070	0	0
T43	369626	369292	0	0
T50	240746	240630	0	0
T61	575230	574982	0	0
T84	298150	298040	0	0
T85	304476	304366	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1968	1968	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T17	2	2	0	0
T31	2	2	0	0
T43	2	2	0	0
T50	2	2	0	0
T61	2	2	0	0
T84	2	2	0	0
T85	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971970586	8454	0	0
T161	475796	0	0	0
T170	98732	0	0	0
T175	153588	2819	0	0
T176	0	2816	0	0
T177	0	2819	0	0
T212	193208	0	0	0
T298	173388	0	0	0
T299	138928	0	0	0
T300	429988	0	0	0
T301	490020	0	0	0
T302	246280	0	0	0
T303	194020	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971970586	8454	0	0
T161	475796	0	0	0
T170	98732	0	0	0
T175	153588	2819	0	0
T176	0	2816	0	0
T177	0	2819	0	0
T212	193208	0	0	0
T298	173388	0	0	0
T299	138928	0	0	0
T300	429988	0	0	0
T301	490020	0	0	0
T302	246280	0	0	0
T303	194020	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971970586	951895072	0	0
T4	308132	308016	0	0
T5	331906	331672	0	0
T6	210494	210374	0	0
T17	1215916	1215362	0	0
T31	230122	230070	0	0
T43	369626	369292	0	0
T50	240746	240630	0	0
T61	575230	574982	0	0
T84	298150	298040	0	0
T85	304476	304366	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971970586	951895072	0	0
T4	308132	308016	0	0
T5	331906	331672	0	0
T6	210494	210374	0	0
T17	1215916	1215362	0	0
T31	230122	230070	0	0
T43	369626	369292	0	0
T50	240746	240630	0	0
T61	575230	574982	0	0
T84	298150	298040	0	0
T85	304476	304366	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971970586	8454	0	0
T161	475796	0	0	0
T170	98732	0	0	0
T175	153588	2819	0	0
T176	0	2816	0	0
T177	0	2819	0	0
T212	193208	0	0	0
T298	173388	0	0	0
T299	138928	0	0	0
T300	429988	0	0	0
T301	490020	0	0	0
T302	246280	0	0	0
T303	194020	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971970586	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971970586	8454	0	0
T161	475796	0	0	0
T170	98732	0	0	0
T175	153588	2819	0	0
T176	0	2816	0	0
T177	0	2819	0	0
T212	193208	0	0	0
T298	173388	0	0	0
T299	138928	0	0	0
T300	429988	0	0	0
T301	490020	0	0	0
T302	246280	0	0	0
T303	194020	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971970586	8454	0	0
T161	475796	0	0	0
T170	98732	0	0	0
T175	153588	2819	0	0
T176	0	2816	0	0
T177	0	2819	0	0
T212	193208	0	0	0
T298	173388	0	0	0
T299	138928	0	0	0
T300	429988	0	0	0
T301	490020	0	0	0
T302	246280	0	0	0
T303	194020	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971970586	8454	0	0
T161	475796	0	0	0
T170	98732	0	0	0
T175	153588	2819	0	0
T176	0	2816	0	0
T177	0	2819	0	0
T212	193208	0	0	0
T298	173388	0	0	0
T299	138928	0	0	0
T300	429988	0	0	0
T301	490020	0	0	0
T302	246280	0	0	0
T303	194020	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971970586	8454	0	0
T161	475796	0	0	0
T170	98732	0	0	0
T175	153588	2819	0	0
T176	0	2816	0	0
T177	0	2819	0	0
T212	193208	0	0	0
T298	173388	0	0	0
T299	138928	0	0	0
T300	429988	0	0	0
T301	490020	0	0	0
T302	246280	0	0	0
T303	194020	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971970586	951895072	0	0
T4	308132	308016	0	0
T5	331906	331672	0	0
T6	210494	210374	0	0
T17	1215916	1215362	0	0
T31	230122	230070	0	0
T43	369626	369292	0	0
T50	240746	240630	0	0
T61	575230	574982	0	0
T84	298150	298040	0	0
T85	304476	304366	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971970586	8454	0	0
T161	475796	0	0	0
T170	98732	0	0	0
T175	153588	2819	0	0
T176	0	2816	0	0
T177	0	2819	0	0
T212	193208	0	0	0
T298	173388	0	0	0
T299	138928	0	0	0
T300	429988	0	0	0
T301	490020	0	0	0
T302	246280	0	0	0
T303	194020	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T175,T176,T177
0	1	Covered	T175,T176,T177
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T175,T176,T177
1	Covered	T175,T176,T177

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T175,T176,T177
1	Covered	T175,T176,T177

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T175,T176,T177
1	1	Covered	T175,T176,T177

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T175,T176,T177
1	0	Covered	T175,T176,T177
1	1	Covered	T175,T176,T177

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T175,T176,T177

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T175,T176,T177
0	Covered	T175,T176,T177

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T175,T176,T177
0	Covered	T175,T176,T177

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	485985293	475947536	0	0
CheckNGreaterZero_A	984	984	0	0
GntImpliesReady_A	485985293	5271	0	0
GntImpliesValid_A	485985293	5271	0	0
GrantKnown_A	485985293	475947536	0	0
IdxKnown_A	485985293	475947536	0	0
IndexIsCorrect_A	485985293	5271	0	0
NoReadyValidNoGrant_A	485985293	0	0	0
Priority_A	485985293	5271	0	0
ReadyAndValidImplyGrant_A	485985293	5271	0	0
ReqAndReadyImplyGrant_A	485985293	5271	0	0
ReqImpliesValid_A	485985293	5271	0	0
ValidKnown_A	485985293	475947536	0	0
gen_data_port_assertion.DataFlow_A	485985293	5271	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	475947536	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	984	984	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T50	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	5271	0	0
T161	237898	0	0	0
T170	49366	0	0	0
T175	76794	1758	0	0
T176	0	1755	0	0
T177	0	1758	0	0
T212	96604	0	0	0
T298	86694	0	0	0
T299	69464	0	0	0
T300	214994	0	0	0
T301	245010	0	0	0
T302	123140	0	0	0
T303	97010	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	5271	0	0
T161	237898	0	0	0
T170	49366	0	0	0
T175	76794	1758	0	0
T176	0	1755	0	0
T177	0	1758	0	0
T212	96604	0	0	0
T298	86694	0	0	0
T299	69464	0	0	0
T300	214994	0	0	0
T301	245010	0	0	0
T302	123140	0	0	0
T303	97010	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	475947536	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	475947536	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	5271	0	0
T161	237898	0	0	0
T170	49366	0	0	0
T175	76794	1758	0	0
T176	0	1755	0	0
T177	0	1758	0	0
T212	96604	0	0	0
T298	86694	0	0	0
T299	69464	0	0	0
T300	214994	0	0	0
T301	245010	0	0	0
T302	123140	0	0	0
T303	97010	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	5271	0	0
T161	237898	0	0	0
T170	49366	0	0	0
T175	76794	1758	0	0
T176	0	1755	0	0
T177	0	1758	0	0
T212	96604	0	0	0
T298	86694	0	0	0
T299	69464	0	0	0
T300	214994	0	0	0
T301	245010	0	0	0
T302	123140	0	0	0
T303	97010	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	5271	0	0
T161	237898	0	0	0
T170	49366	0	0	0
T175	76794	1758	0	0
T176	0	1755	0	0
T177	0	1758	0	0
T212	96604	0	0	0
T298	86694	0	0	0
T299	69464	0	0	0
T300	214994	0	0	0
T301	245010	0	0	0
T302	123140	0	0	0
T303	97010	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	5271	0	0
T161	237898	0	0	0
T170	49366	0	0	0
T175	76794	1758	0	0
T176	0	1755	0	0
T177	0	1758	0	0
T212	96604	0	0	0
T298	86694	0	0	0
T299	69464	0	0	0
T300	214994	0	0	0
T301	245010	0	0	0
T302	123140	0	0	0
T303	97010	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	5271	0	0
T161	237898	0	0	0
T170	49366	0	0	0
T175	76794	1758	0	0
T176	0	1755	0	0
T177	0	1758	0	0
T212	96604	0	0	0
T298	86694	0	0	0
T299	69464	0	0	0
T300	214994	0	0	0
T301	245010	0	0	0
T302	123140	0	0	0
T303	97010	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	475947536	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	5271	0	0
T161	237898	0	0	0
T170	49366	0	0	0
T175	76794	1758	0	0
T176	0	1755	0	0
T177	0	1758	0	0
T212	96604	0	0	0
T298	86694	0	0	0
T299	69464	0	0	0
T300	214994	0	0	0
T301	245010	0	0	0
T302	123140	0	0	0
T303	97010	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T175,T176,T177
0	1	Covered	T175,T176,T177
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T175,T176,T177
1	Covered	T175,T176,T177

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T175,T176,T177
1	Covered	T175,T176,T177

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T175,T176,T177
1	1	Covered	T175,T176,T177

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T175,T176,T177
1	0	Covered	T175,T176,T177
1	1	Covered	T175,T176,T177

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T175,T176,T177

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T175,T176,T177
0	Covered	T175,T176,T177

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T175,T176,T177
0	Covered	T175,T176,T177

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	485985293	475947536	0	0
CheckNGreaterZero_A	984	984	0	0
GntImpliesReady_A	485985293	3183	0	0
GntImpliesValid_A	485985293	3183	0	0
GrantKnown_A	485985293	475947536	0	0
IdxKnown_A	485985293	475947536	0	0
IndexIsCorrect_A	485985293	3183	0	0
NoReadyValidNoGrant_A	485985293	0	0	0
Priority_A	485985293	3183	0	0
ReadyAndValidImplyGrant_A	485985293	3183	0	0
ReqAndReadyImplyGrant_A	485985293	3183	0	0
ReqImpliesValid_A	485985293	3183	0	0
ValidKnown_A	485985293	475947536	0	0
gen_data_port_assertion.DataFlow_A	485985293	3183	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	475947536	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	984	984	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T50	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	3183	0	0
T161	237898	0	0	0
T170	49366	0	0	0
T175	76794	1061	0	0
T176	0	1061	0	0
T177	0	1061	0	0
T212	96604	0	0	0
T298	86694	0	0	0
T299	69464	0	0	0
T300	214994	0	0	0
T301	245010	0	0	0
T302	123140	0	0	0
T303	97010	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	3183	0	0
T161	237898	0	0	0
T170	49366	0	0	0
T175	76794	1061	0	0
T176	0	1061	0	0
T177	0	1061	0	0
T212	96604	0	0	0
T298	86694	0	0	0
T299	69464	0	0	0
T300	214994	0	0	0
T301	245010	0	0	0
T302	123140	0	0	0
T303	97010	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	475947536	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	475947536	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	3183	0	0
T161	237898	0	0	0
T170	49366	0	0	0
T175	76794	1061	0	0
T176	0	1061	0	0
T177	0	1061	0	0
T212	96604	0	0	0
T298	86694	0	0	0
T299	69464	0	0	0
T300	214994	0	0	0
T301	245010	0	0	0
T302	123140	0	0	0
T303	97010	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	3183	0	0
T161	237898	0	0	0
T170	49366	0	0	0
T175	76794	1061	0	0
T176	0	1061	0	0
T177	0	1061	0	0
T212	96604	0	0	0
T298	86694	0	0	0
T299	69464	0	0	0
T300	214994	0	0	0
T301	245010	0	0	0
T302	123140	0	0	0
T303	97010	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	3183	0	0
T161	237898	0	0	0
T170	49366	0	0	0
T175	76794	1061	0	0
T176	0	1061	0	0
T177	0	1061	0	0
T212	96604	0	0	0
T298	86694	0	0	0
T299	69464	0	0	0
T300	214994	0	0	0
T301	245010	0	0	0
T302	123140	0	0	0
T303	97010	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	3183	0	0
T161	237898	0	0	0
T170	49366	0	0	0
T175	76794	1061	0	0
T176	0	1061	0	0
T177	0	1061	0	0
T212	96604	0	0	0
T298	86694	0	0	0
T299	69464	0	0	0
T300	214994	0	0	0
T301	245010	0	0	0
T302	123140	0	0	0
T303	97010	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	3183	0	0
T161	237898	0	0	0
T170	49366	0	0	0
T175	76794	1061	0	0
T176	0	1061	0	0
T177	0	1061	0	0
T212	96604	0	0	0
T298	86694	0	0	0
T299	69464	0	0	0
T300	214994	0	0	0
T301	245010	0	0	0
T302	123140	0	0	0
T303	97010	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	475947536	0	0
T4	154066	154008	0	0
T5	165953	165836	0	0
T6	105247	105187	0	0
T17	607958	607681	0	0
T31	115061	115035	0	0
T43	184813	184646	0	0
T50	120373	120315	0	0
T61	287615	287491	0	0
T84	149075	149020	0	0
T85	152238	152183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485985293	3183	0	0
T161	237898	0	0	0
T170	49366	0	0	0
T175	76794	1061	0	0
T176	0	1061	0	0
T177	0	1061	0	0
T212	96604	0	0	0
T298	86694	0	0	0
T299	69464	0	0	0
T300	214994	0	0	0
T301	245010	0	0	0
T302	123140	0	0	0
T303	97010	0	0	0