Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.41	99.34	100.00			98.31	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	984	984	0	0
OutputsKnown_A	120940044	120282222	0	0
gen_no_flops.OutputDelay_A	120940044	120282222	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	984	984	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T50	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120940044	120282222	0	0
T4	37796	37355	0	0
T5	41191	40576	0	0
T6	284672	284073	0	0
T17	148755	147790	0	0
T31	280936	280109	0	0
T43	46917	46046	0	0
T50	29881	29258	0	0
T61	70130	69765	0	0
T84	40733	40149	0	0
T85	41454	40550	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120940044	120282222	0	0
T4	37796	37355	0	0
T5	41191	40576	0	0
T6	284672	284073	0	0
T17	148755	147790	0	0
T31	280936	280109	0	0
T43	46917	46046	0	0
T50	29881	29258	0	0
T61	70130	69765	0	0
T84	40733	40149	0	0
T85	41454	40550	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	984	984	0	0
OutputsKnown_A	120940044	120282222	0	0
gen_no_flops.OutputDelay_A	120940044	120282222	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	984	984	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T50	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120940044	120282222	0	0
T4	37796	37355	0	0
T5	41191	40576	0	0
T6	284672	284073	0	0
T17	148755	147790	0	0
T31	280936	280109	0	0
T43	46917	46046	0	0
T50	29881	29258	0	0
T61	70130	69765	0	0
T84	40733	40149	0	0
T85	41454	40550	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120940044	120282222	0	0
T4	37796	37355	0	0
T5	41191	40576	0	0
T6	284672	284073	0	0
T17	148755	147790	0	0
T31	280936	280109	0	0
T43	46917	46046	0	0
T50	29881	29258	0	0
T61	70130	69765	0	0
T84	40733	40149	0	0
T85	41454	40550	0	0