Unified Coverage Report :: Module :: chip_earlgrey_asic

Module : chip_earlgrey_asic

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.90	80.00	100.00	95.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	92.83	80.00	100.00	98.48

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.83	80.00	100.00	98.48

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.45	95.57	94.38	95.52		95.30	96.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
top_earlgrey	95.41	95.50	93.94	95.50		95.11	97.02
u_ast	94.79			94.79
u_padring	97.80	99.21	99.81	96.57		99.60	93.81
u_prim_usb_diff_rx	96.30	100.00	88.89			100.00

Line Coverage for Module : chip_earlgrey_asic

	Line No.	Total	Covered	Percent
TOTAL		25	20	80.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	787	1	0	0.00
CONT_ASSIGN	798	1	0	0.00
CONT_ASSIGN	823	1	0	0.00
CONT_ASSIGN	830	1	0	0.00
CONT_ASSIGN	837	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	846	1	1	100.00
CONT_ASSIGN	848	1	1	100.00
CONT_ASSIGN	852	1	0	0.00
CONT_ASSIGN	855	1	1	100.00
CONT_ASSIGN	1019	1	1	100.00
CONT_ASSIGN	1020	1	1	100.00
CONT_ASSIGN	1021	1	1	100.00
CONT_ASSIGN	1022	1	1	100.00
CONT_ASSIGN	1029	1	1	100.00
CONT_ASSIGN	1046	1	1	100.00
CONT_ASSIGN	1047	1	1	100.00
CONT_ASSIGN	1048	1	1	100.00
CONT_ASSIGN	1049	1	1	100.00
CONT_ASSIGN	1053	1	1	100.00
CONT_ASSIGN	1054	1	1	100.00
CONT_ASSIGN	1055	1	1	100.00
CONT_ASSIGN	1056	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
212	1	1
213	1	1
787	0	1
798	0	1
823	0	1
830	0	1
837	1	1
840	1	1
846	1	1
848	1	1
852	0	1
855	1	1
1019	1	1
1020	1	1
1021	1	1
1022	1	1
1029	1	1
1046	1	1
1047	1	1
1048	1	1
1049	1	1
1053	1	1
1054	1	1
1055	1	1
1056	1	1

---

Cond Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T43,T84

---

Toggle Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Totals	70	64	91.43
Total Bits	140	134	95.71
Total Bits 0->1	70	70	100.00
Total Bits 1->0	70	64	91.43

Ports	70	64	91.43
Port Bits	140	134	95.71
Port Bits 0->1	70	70	100.00
Port Bits 1->0	70	64	91.43

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
POR_N	Yes	Yes	T18,T19,T20	Yes	T4,T5,T6	INOUT
USB_P	Yes	Yes	T28,T34,T35	Yes	T28,T34,T35	INOUT
USB_N	Yes	Yes	T28,T34,T35	Yes	T21,T28,T34	INOUT
CC1	No	No		Yes	T21,T22,T23	INOUT
CC2	No	No		Yes	T21,T22,T23	INOUT
FLASH_TEST_VOLT	No	No		Yes	T21,T22,T23	INOUT
FLASH_TEST_MODE0	No	No		Yes	T21,T22,T23	INOUT
FLASH_TEST_MODE1	No	No		Yes	T21,T22,T23	INOUT
OTP_EXT_VOLT	No	No		Yes	T21,T22,T23	INOUT
SPI_HOST_D0	Yes	Yes	T24,T25,T26	Yes	T21,T24,T25	INOUT
SPI_HOST_D1	Yes	Yes	T24,T25,T26	Yes	T21,T24,T25	INOUT
SPI_HOST_D2	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INOUT
SPI_HOST_D3	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INOUT
SPI_HOST_CLK	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INOUT
SPI_HOST_CS_L	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INOUT
SPI_DEV_D0	Yes	Yes	T50,T20,T24	Yes	T50,T20,T24	INOUT
SPI_DEV_D1	Yes	Yes	T50,T20,T24	Yes	T50,T20,T24	INOUT
SPI_DEV_D2	Yes	Yes	T24,T25,T26	Yes	T21,T24,T25	INOUT
SPI_DEV_D3	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INOUT
SPI_DEV_CLK	Yes	Yes	T50,T20,T24	Yes	T50,T20,T21	INOUT
SPI_DEV_CS_L	Yes	Yes	T20,T21,T24	Yes	T20,T21,T24	INOUT
IOR8	Yes	Yes	T31,T32,T196	Yes	T31,T21,T32	INOUT
IOR9	Yes	Yes	T31,T32,T196	Yes	T31,T47,T32	INOUT
IOA0	Yes	Yes	T27,T2,T3	Yes	T27,T2,T3	INOUT
IOA1	Yes	Yes	T27,T2,T3	Yes	T27,T2,T3	INOUT
IOA2	Yes	Yes	T93,T27,T2	Yes	T93,T27,T2	INOUT
IOA3	Yes	Yes	T27,T2,T3	Yes	T27,T2,T3	INOUT
IOA4	Yes	Yes	T203,T27,T109	Yes	T203,T27,T109	INOUT
IOA5	Yes	Yes	T203,T27,T109	Yes	T203,T27,T109	INOUT
IOA6	Yes	Yes	T27,T2,T3	Yes	T27,T2,T3	INOUT
IOA7	Yes	Yes	T50,T27,T2	Yes	T50,T27,T2	INOUT
IOA8	Yes	Yes	T27,T2,T3	Yes	T27,T2,T3	INOUT
IOB0	Yes	Yes	T44,T40,T41	Yes	T44,T22,T23	INOUT
IOB1	Yes	Yes	T44,T40,T41	Yes	T44,T40,T41	INOUT
IOB2	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INOUT
IOB3	Yes	Yes	T31,T32,T44	Yes	T31,T32,T44	INOUT
IOB4	Yes	Yes	T208,T44,T209	Yes	T208,T44,T209	INOUT
IOB5	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	INOUT
IOB6	Yes	Yes	T31,T27,T32	Yes	T31,T21,T27	INOUT
IOB7	Yes	Yes	T1,T27,T37	Yes	T1,T47,T27	INOUT
IOB8	Yes	Yes	T31,T27,T32	Yes	T21,T27,T196	INOUT
IOB9	Yes	Yes	T31,T27,T32	Yes	T27,T214,T212	INOUT
IOB10	Yes	Yes	T93,T27,T215	Yes	T93,T27,T215	INOUT
IOB11	Yes	Yes	T93,T27,T215	Yes	T93,T27,T215	INOUT
IOB12	Yes	Yes	T93,T27,T215	Yes	T93,T27,T215	INOUT
IOC0	Yes	Yes	T18,T19,T20	Yes	T20,T21,T216	INOUT
IOC1	Yes	Yes	T20,T216,T217	Yes	T20,T216,T217	INOUT
IOC2	Yes	Yes	T20,T216,T217	Yes	T20,T21,T216	INOUT
IOC3	Yes	Yes	T94,T218,T110	Yes	T94,T218,T110	INOUT
IOC4	Yes	Yes	T18,T19,T94	Yes	T18,T19,T94	INOUT
IOC5	Yes	Yes	T20,T219,T363	Yes	T20,T219,T66	INOUT
IOC6	Yes	Yes	T57,T55,T56	Yes	T57,T55,T56	INOUT
IOC7	Yes	Yes	T31,T32,T196	Yes	T31,T21,T32	INOUT
IOC8	Yes	Yes	T219,T66,T68	Yes	T20,T21,T219	INOUT
IOC9	Yes	Yes	T31,T47,T27	Yes	T31,T21,T47	INOUT
IOC10	Yes	Yes	T93,T27,T215	Yes	T93,T21,T27	INOUT
IOC11	Yes	Yes	T93,T27,T215	Yes	T93,T27,T215	INOUT
IOC12	Yes	Yes	T93,T27,T215	Yes	T93,T27,T215	INOUT
IOR0	Yes	Yes	T20,T57,T55	Yes	T20,T57,T55	INOUT
IOR1	Yes	Yes	T20,T57,T55	Yes	T20,T57,T55	INOUT
IOR2	Yes	Yes	T20,T57,T55	Yes	T20,T57,T55	INOUT
IOR3	Yes	Yes	T20,T57,T55	Yes	T20,T57,T55	INOUT
IOR4	Yes	Yes	T20,T55,T56	Yes	T20,T57,T21	INOUT
IOR5	Yes	Yes	T27,T33,T37	Yes	T27,T33,T37	INOUT
IOR6	Yes	Yes	T27,T37,T211	Yes	T27,T33,T37	INOUT
IOR7	Yes	Yes	T27,T37,T211	Yes	T27,T37,T211	INOUT
IOR10	Yes	Yes	T27,T37,T211	Yes	T21,T27,T37	INOUT
IOR11	Yes	Yes	T27,T37,T211	Yes	T27,T37,T211	INOUT
IOR12	Yes	Yes	T27,T37,T211	Yes	T21,T27,T37	INOUT
IOR13	Yes	Yes	T1,T27,T222	Yes	T1,T27,T222	INOUT

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		25	20	80.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	787	1	0	0.00
CONT_ASSIGN	798	1	0	0.00
CONT_ASSIGN	823	1	0	0.00
CONT_ASSIGN	830	1	0	0.00
CONT_ASSIGN	837	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	846	1	1	100.00
CONT_ASSIGN	848	1	1	100.00
CONT_ASSIGN	852	1	0	0.00
CONT_ASSIGN	855	1	1	100.00
CONT_ASSIGN	1019	1	1	100.00
CONT_ASSIGN	1020	1	1	100.00
CONT_ASSIGN	1021	1	1	100.00
CONT_ASSIGN	1022	1	1	100.00
CONT_ASSIGN	1029	1	1	100.00
CONT_ASSIGN	1046	1	1	100.00
CONT_ASSIGN	1047	1	1	100.00
CONT_ASSIGN	1048	1	1	100.00
CONT_ASSIGN	1049	1	1	100.00
CONT_ASSIGN	1053	1	1	100.00
CONT_ASSIGN	1054	1	1	100.00
CONT_ASSIGN	1055	1	1	100.00
CONT_ASSIGN	1056	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
212	1	1
213	1	1
787	0	1
798	0	1
823	0	1
830	0	1
837	1	1
840	1	1
846	1	1
848	1	1
852	0	1
855	1	1
1019	1	1
1020	1	1
1021	1	1
1022	1	1
1029	1	1
1046	1	1
1047	1	1
1048	1	1
1049	1	1
1053	1	1
1054	1	1
1055	1	1
1056	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T43,T84

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	66	64	96.97
Total Bits	132	130	98.48
Total Bits 0->1	66	66	100.00
Total Bits 1->0	66	64	96.97

Ports	66	64	96.97
Port Bits	132	130	98.48
Port Bits 0->1	66	66	100.00
Port Bits 1->0	66	64	96.97

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
POR_N	Yes	Yes	T18,T19,T20	Yes	T4,T5,T6	INOUT
USB_P	Yes	Yes	T28,T34,T35	Yes	T28,T34,T35	INOUT
USB_N	Yes	Yes	T28,T34,T35	Yes	T21,T28,T34	INOUT
CC1	No	No		Yes	T21,T22,T23	INOUT
CC2	No	No		Yes	T21,T22,T23	INOUT
FLASH_TEST_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE0[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE1[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
OTP_EXT_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
SPI_HOST_D0	Yes	Yes	T24,T25,T26	Yes	T21,T24,T25	INOUT
SPI_HOST_D1	Yes	Yes	T24,T25,T26	Yes	T21,T24,T25	INOUT
SPI_HOST_D2	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INOUT
SPI_HOST_D3	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INOUT
SPI_HOST_CLK	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INOUT
SPI_HOST_CS_L	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INOUT
SPI_DEV_D0	Yes	Yes	T50,T20,T24	Yes	T50,T20,T24	INOUT
SPI_DEV_D1	Yes	Yes	T50,T20,T24	Yes	T50,T20,T24	INOUT
SPI_DEV_D2	Yes	Yes	T24,T25,T26	Yes	T21,T24,T25	INOUT
SPI_DEV_D3	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INOUT
SPI_DEV_CLK	Yes	Yes	T50,T20,T24	Yes	T50,T20,T21	INOUT
SPI_DEV_CS_L	Yes	Yes	T20,T21,T24	Yes	T20,T21,T24	INOUT
IOR8	Yes	Yes	T31,T32,T196	Yes	T31,T21,T32	INOUT
IOR9	Yes	Yes	T31,T32,T196	Yes	T31,T47,T32	INOUT
IOA0	Yes	Yes	T27,T2,T3	Yes	T27,T2,T3	INOUT
IOA1	Yes	Yes	T27,T2,T3	Yes	T27,T2,T3	INOUT
IOA2	Yes	Yes	T93,T27,T2	Yes	T93,T27,T2	INOUT
IOA3	Yes	Yes	T27,T2,T3	Yes	T27,T2,T3	INOUT
IOA4	Yes	Yes	T203,T27,T109	Yes	T203,T27,T109	INOUT
IOA5	Yes	Yes	T203,T27,T109	Yes	T203,T27,T109	INOUT
IOA6	Yes	Yes	T27,T2,T3	Yes	T27,T2,T3	INOUT
IOA7	Yes	Yes	T50,T27,T2	Yes	T50,T27,T2	INOUT
IOA8	Yes	Yes	T27,T2,T3	Yes	T27,T2,T3	INOUT
IOB0	Yes	Yes	T44,T40,T41	Yes	T44,T22,T23	INOUT
IOB1	Yes	Yes	T44,T40,T41	Yes	T44,T40,T41	INOUT
IOB2	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INOUT
IOB3	Yes	Yes	T31,T32,T44	Yes	T31,T32,T44	INOUT
IOB4	Yes	Yes	T208,T44,T209	Yes	T208,T44,T209	INOUT
IOB5	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	INOUT
IOB6	Yes	Yes	T31,T27,T32	Yes	T31,T21,T27	INOUT
IOB7	Yes	Yes	T1,T27,T37	Yes	T1,T47,T27	INOUT
IOB8	Yes	Yes	T31,T27,T32	Yes	T21,T27,T196	INOUT
IOB9	Yes	Yes	T31,T27,T32	Yes	T27,T214,T212	INOUT
IOB10	Yes	Yes	T93,T27,T215	Yes	T93,T27,T215	INOUT
IOB11	Yes	Yes	T93,T27,T215	Yes	T93,T27,T215	INOUT
IOB12	Yes	Yes	T93,T27,T215	Yes	T93,T27,T215	INOUT
IOC0	Yes	Yes	T18,T19,T20	Yes	T20,T21,T216	INOUT
IOC1	Yes	Yes	T20,T216,T217	Yes	T20,T216,T217	INOUT
IOC2	Yes	Yes	T20,T216,T217	Yes	T20,T21,T216	INOUT
IOC3	Yes	Yes	T94,T218,T110	Yes	T94,T218,T110	INOUT
IOC4	Yes	Yes	T18,T19,T94	Yes	T18,T19,T94	INOUT
IOC5	Yes	Yes	T20,T219,T363	Yes	T20,T219,T66	INOUT
IOC6	Yes	Yes	T57,T55,T56	Yes	T57,T55,T56	INOUT
IOC7	Yes	Yes	T31,T32,T196	Yes	T31,T21,T32	INOUT
IOC8	Yes	Yes	T219,T66,T68	Yes	T20,T21,T219	INOUT
IOC9	Yes	Yes	T31,T47,T27	Yes	T31,T21,T47	INOUT
IOC10	Yes	Yes	T93,T27,T215	Yes	T93,T21,T27	INOUT
IOC11	Yes	Yes	T93,T27,T215	Yes	T93,T27,T215	INOUT
IOC12	Yes	Yes	T93,T27,T215	Yes	T93,T27,T215	INOUT
IOR0	Yes	Yes	T20,T57,T55	Yes	T20,T57,T55	INOUT
IOR1	Yes	Yes	T20,T57,T55	Yes	T20,T57,T55	INOUT
IOR2	Yes	Yes	T20,T57,T55	Yes	T20,T57,T55	INOUT
IOR3	Yes	Yes	T20,T57,T55	Yes	T20,T57,T55	INOUT
IOR4	Yes	Yes	T20,T55,T56	Yes	T20,T57,T21	INOUT
IOR5	Yes	Yes	T27,T33,T37	Yes	T27,T33,T37	INOUT
IOR6	Yes	Yes	T27,T37,T211	Yes	T27,T33,T37	INOUT
IOR7	Yes	Yes	T27,T37,T211	Yes	T27,T37,T211	INOUT
IOR10	Yes	Yes	T27,T37,T211	Yes	T21,T27,T37	INOUT
IOR11	Yes	Yes	T27,T37,T211	Yes	T27,T37,T211	INOUT
IOR12	Yes	Yes	T27,T37,T211	Yes	T21,T27,T37	INOUT
IOR13	Yes	Yes	T1,T27,T222	Yes	T1,T27,T222	INOUT