Group : chip_env_pkg::chip_alert_cg_wrap::alert_cg
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Group : chip_env_pkg::chip_alert_cg_wrap::alert_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_chip_env_0.1/chip_env_cov.sv

65 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
adc_ctrl_aon_fatal_fault 100.00 1 100 1 64 64
aes_fatal_fault 100.00 1 100 1 64 64
aes_recov_ctrl_update_err 100.00 1 100 1 64 64
aon_timer_aon_fatal_fault 100.00 1 100 1 64 64
clkmgr_aon_fatal_fault 100.00 1 100 1 64 64
clkmgr_aon_recov_fault 100.00 1 100 1 64 64
csrng_fatal_alert 100.00 1 100 1 64 64
csrng_recov_alert 100.00 1 100 1 64 64
edn0_fatal_alert 100.00 1 100 1 64 64
edn0_recov_alert 100.00 1 100 1 64 64
edn1_fatal_alert 100.00 1 100 1 64 64
edn1_recov_alert 100.00 1 100 1 64 64
entropy_src_fatal_alert 100.00 1 100 1 64 64
entropy_src_recov_alert 100.00 1 100 1 64 64
flash_ctrl_fatal_err 100.00 1 100 1 64 64
flash_ctrl_fatal_prim_flash_alert 100.00 1 100 1 64 64
flash_ctrl_fatal_std_err 100.00 1 100 1 64 64
flash_ctrl_recov_err 100.00 1 100 1 64 64
flash_ctrl_recov_prim_flash_alert 100.00 1 100 1 64 64
gpio_fatal_fault 100.00 1 100 1 64 64
hmac_fatal_fault 100.00 1 100 1 64 64
i2c0_fatal_fault 100.00 1 100 1 64 64
i2c1_fatal_fault 100.00 1 100 1 64 64
i2c2_fatal_fault 100.00 1 100 1 64 64
keymgr_fatal_fault_err 100.00 1 100 1 64 64
keymgr_recov_operation_err 100.00 1 100 1 64 64
kmac_fatal_fault_err 100.00 1 100 1 64 64
kmac_recov_operation_err 100.00 1 100 1 64 64
lc_ctrl_fatal_bus_integ_error 100.00 1 100 1 64 64
lc_ctrl_fatal_prog_error 100.00 1 100 1 64 64
lc_ctrl_fatal_state_error 100.00 1 100 1 64 64
otbn_fatal 100.00 1 100 1 64 64
otbn_recov 100.00 1 100 1 64 64
otp_ctrl_fatal_bus_integ_error 100.00 1 100 1 64 64
otp_ctrl_fatal_check_error 100.00 1 100 1 64 64
otp_ctrl_fatal_macro_error 100.00 1 100 1 64 64
otp_ctrl_fatal_prim_otp_alert 100.00 1 100 1 64 64
otp_ctrl_recov_prim_otp_alert 100.00 1 100 1 64 64
pattgen_fatal_fault 100.00 1 100 1 64 64
pinmux_aon_fatal_fault 100.00 1 100 1 64 64
pwm_aon_fatal_fault 100.00 1 100 1 64 64
pwrmgr_aon_fatal_fault 100.00 1 100 1 64 64
rom_ctrl_fatal 100.00 1 100 1 64 64
rstmgr_aon_fatal_cnsty_fault 100.00 1 100 1 64 64
rstmgr_aon_fatal_fault 100.00 1 100 1 64 64
rv_core_ibex_fatal_hw_err 100.00 1 100 1 64 64
rv_core_ibex_fatal_sw_err 100.00 1 100 1 64 64
rv_core_ibex_recov_hw_err 100.00 1 100 1 64 64
rv_core_ibex_recov_sw_err 100.00 1 100 1 64 64
rv_dm_fatal_fault 100.00 1 100 1 64 64
rv_plic_fatal_fault 100.00 1 100 1 64 64
rv_timer_fatal_fault 100.00 1 100 1 64 64
sensor_ctrl_aon_fatal_alert 100.00 1 100 1 64 64
sensor_ctrl_aon_recov_alert 100.00 1 100 1 64 64
spi_device_fatal_fault 100.00 1 100 1 64 64
spi_host0_fatal_fault 100.00 1 100 1 64 64
spi_host1_fatal_fault 100.00 1 100 1 64 64
sram_ctrl_main_fatal_error 100.00 1 100 1 64 64
sram_ctrl_ret_aon_fatal_error 100.00 1 100 1 64 64
sysrst_ctrl_aon_fatal_fault 100.00 1 100 1 64 64
uart0_fatal_fault 100.00 1 100 1 64 64
uart1_fatal_fault 100.00 1 100 1 64 64
uart2_fatal_fault 100.00 1 100 1 64 64
uart3_fatal_fault 100.00 1 100 1 64 64
usbdev_fatal_fault 100.00 1 100 1 64 64




Group Instance : adc_ctrl_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance adc_ctrl_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance adc_ctrl_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : aes_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance aes_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance aes_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : aes_recov_ctrl_update_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance aes_recov_ctrl_update_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance aes_recov_ctrl_update_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : aon_timer_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance aon_timer_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance aon_timer_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : clkmgr_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance clkmgr_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance clkmgr_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : clkmgr_aon_recov_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance clkmgr_aon_recov_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance clkmgr_aon_recov_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : csrng_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance csrng_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance csrng_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : csrng_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance csrng_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance csrng_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn0_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn0_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn0_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn0_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn0_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn0_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn1_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn1_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn1_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn1_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn1_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn1_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : entropy_src_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance entropy_src_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance entropy_src_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : entropy_src_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance entropy_src_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance entropy_src_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_fatal_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_fatal_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_fatal_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_fatal_prim_flash_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_fatal_prim_flash_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_fatal_prim_flash_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_fatal_std_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_fatal_std_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_fatal_std_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_recov_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_recov_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_recov_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_recov_prim_flash_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_recov_prim_flash_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_recov_prim_flash_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : gpio_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance gpio_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance gpio_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : hmac_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance hmac_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance hmac_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : i2c0_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c0_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance i2c0_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : i2c1_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c1_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance i2c1_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : i2c2_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c2_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance i2c2_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : keymgr_fatal_fault_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance keymgr_fatal_fault_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance keymgr_fatal_fault_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : keymgr_recov_operation_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance keymgr_recov_operation_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance keymgr_recov_operation_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : kmac_fatal_fault_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance kmac_fatal_fault_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance kmac_fatal_fault_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : kmac_recov_operation_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance kmac_recov_operation_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance kmac_recov_operation_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : lc_ctrl_fatal_bus_integ_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lc_ctrl_fatal_bus_integ_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance lc_ctrl_fatal_bus_integ_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : lc_ctrl_fatal_prog_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lc_ctrl_fatal_prog_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance lc_ctrl_fatal_prog_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : lc_ctrl_fatal_state_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lc_ctrl_fatal_state_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance lc_ctrl_fatal_state_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otbn_fatal
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otbn_fatal

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otbn_fatal
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otbn_recov
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otbn_recov

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otbn_recov
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_bus_integ_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_bus_integ_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_bus_integ_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_check_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_check_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_check_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_macro_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_macro_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_macro_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_prim_otp_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_prim_otp_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_prim_otp_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_recov_prim_otp_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_recov_prim_otp_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_recov_prim_otp_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pattgen_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pattgen_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pattgen_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pinmux_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pinmux_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pinmux_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pwm_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pwm_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pwm_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pwrmgr_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pwrmgr_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pwrmgr_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rom_ctrl_fatal
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rom_ctrl_fatal

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rom_ctrl_fatal
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rstmgr_aon_fatal_cnsty_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rstmgr_aon_fatal_cnsty_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rstmgr_aon_fatal_cnsty_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rstmgr_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rstmgr_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rstmgr_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_fatal_hw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_fatal_hw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_fatal_hw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_fatal_sw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_fatal_sw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_fatal_sw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_recov_hw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_recov_hw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_recov_hw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_recov_sw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_recov_sw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_recov_sw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_dm_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_dm_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_dm_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_plic_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_plic_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_plic_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_timer_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_timer_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sensor_ctrl_aon_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sensor_ctrl_aon_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sensor_ctrl_aon_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sensor_ctrl_aon_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sensor_ctrl_aon_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sensor_ctrl_aon_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : spi_device_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance spi_device_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : spi_host0_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_host0_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance spi_host0_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : spi_host1_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_host1_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance spi_host1_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sram_ctrl_main_fatal_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sram_ctrl_main_fatal_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sram_ctrl_main_fatal_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sram_ctrl_ret_aon_fatal_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sram_ctrl_ret_aon_fatal_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sram_ctrl_ret_aon_fatal_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sysrst_ctrl_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sysrst_ctrl_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart0_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart0_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart0_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart1_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart1_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart1_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart2_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart2_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart2_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart3_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart3_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart3_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : usbdev_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance usbdev_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance usbdev_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1033 1 T60 1 T80 42 T684 821


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 119354 1 T18 586 T46 589 T47 588


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 175 1 T60 1 T80 40 T82 38


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 6119 1 T18 811 T60 1 T80 41


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3143 1 T60 1 T80 43 T369 811


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 815 1 T60 1 T80 37 T273 101


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5800 1 T46 1720 T60 1 T80 41


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 194 1 T60 1 T80 57 T37 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4741 1 T60 1 T80 39 T32 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 183 1 T60 1 T80 49 T470 2


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4742 1 T60 1 T382 1074 T80 48


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 200 1 T60 1 T80 52 T82 42


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 9811 1 T60 1 T80 44 T32 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 200 1 T60 1 T80 49 T32 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 7337 1 T60 1 T80 44 T350 1706


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5204 1 T60 1 T80 33 T82 35


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 8827 1 T60 1 T80 47 T224 1730


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 394 1 T60 1 T80 44 T106 5


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 166 1 T60 1 T80 40 T82 35


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3337 1 T60 1 T80 53 T109 503


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 6485 1 T60 1 T80 43 T685 1716


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3093 1 T60 1 T80 38 T403 515


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2342 1 T60 1 T80 48 T248 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3185 1 T47 813 T357 821 T60 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3608 1 T60 1 T80 38 T32 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 189 1 T60 1 T80 41 T32 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 120590 1 T18 586 T46 589 T47 588


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 219 1 T60 1 T80 50 T32 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5115 1 T60 1 T80 34 T270 817


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 199 1 T60 1 T80 40 T248 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5089 1 T60 1 T80 56 T163 817


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1394360 1 T18 586 T46 589 T47 588


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 188 1 T60 1 T147 1 T80 46


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3959 1 T60 1 T80 45 T159 535


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 53281 1 T18 276 T46 279 T47 279


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1017 1 T60 1 T80 51 T157 810


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2073 1 T60 1 T80 34 T82 48


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 188 1 T60 1 T80 44 T82 27


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1788 1 T60 1 T80 40 T682 536


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5265 1 T60 1 T80 46 T81 817


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3679 1 T294 817 T60 1 T80 46


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 7825 1 T115 1 T295 1 T60 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2979 1 T60 1 T80 46 T82 32


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2657 1 T60 1 T80 46 T720 812


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 6398 1 T316 530 T60 1 T356 822


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 36197 1 T178 243 T60 1 T117 277


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 6868 1 T60 1 T80 49 T82 44


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 125 1 T60 1 T80 23 T82 17


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 296 1 T60 1 T80 48 T248 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 190 1 T80 45 T82 41 T83 42


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4092 1 T315 1 T60 1 T80 37


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1786 1 T60 1 T80 42 T82 33


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4125 1 T60 1 T80 44 T95 55


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 30200 1 T60 1 T121 1 T80 41


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3579 1 T60 1 T80 48 T213 808


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5140 1 T60 1 T80 44 T225 1692


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3998 1 T60 1 T80 45 T413 817


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1915 1 T60 1 T80 50 T82 31


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 207 1 T60 1 T80 37 T82 37


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2343 1 T60 1 T80 44 T683 528


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4194 1 T63 521 T60 1 T80 40


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3106 1 T60 1 T80 44 T99 521


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5295 1 T60 1 T80 38 T248 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3380 1 T60 1 T80 44 T248 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3219 1 T60 1 T80 38 T32 1

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