Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3606990	1			T153	30		T76	1196		T77	11099
values[2]	714041	1			T153	48		T76	463		T77	2182
values[3]	102014	1			T153	16		T76	192		T77	148
values[4]	53085	1			T153	9		T76	7		T77	79
values[5]	35640	1			T153	10		T77	72		T444	5
values[6]	26988	1			T153	15		T77	68		T444	5
values[7]	21989	1			T153	18		T77	51		T444	5
values[8]	19080	1			T153	22		T77	56		T444	5
values[9]	16924	1			T153	8		T77	68		T444	5
values[10]	15447	1			T153	3		T77	56		T444	5
values[11]	14425	1			T153	6		T77	53		T444	5
values[12]	13493	1			T153	9		T77	56		T444	5
values[13]	12907	1			T153	1		T77	69		T444	5
values[14]	12080	1			T77	57		T444	5		T435	7
values[15]	11564	1			T77	46		T444	5		T435	4
values[16]	10880	1			T77	41		T444	6		T435	7
values[17]	10569	1			T77	51		T444	5		T435	13
values[18]	10263	1			T77	72		T444	5		T435	2
values[19]	9915	1			T77	51		T444	5		T435	2
values[20]	9448	1			T77	40		T444	5		T435	5
values[21]	9111	1			T77	24		T444	5		T435	3
values[22]	9022	1			T77	25		T444	5		T435	11
values[23]	8605	1			T77	20		T444	5		T435	1
values[24]	8681	1			T77	23		T444	6		T435	1
values[25]	8489	1			T77	24		T444	6		T435	1
values[26]	8018	1			T77	30		T444	5		T435	11
values[27]	7642	1			T77	19		T444	5		T435	13
values[28]	7488	1			T77	43		T444	5		T435	14
values[29]	7088	1			T77	42		T444	5		T435	12
values[30]	6372	1			T77	34		T444	5		T435	4
values[31]	6001	1			T77	17		T444	5		T435	2
values[32]	5462	1			T77	12		T444	5		T435	3
values[33]	5022	1			T77	11		T444	5		T435	2
values[34]	4797	1			T77	10		T444	6		T435	2
values[35]	4453	1			T77	6		T444	5		T435	2
values[36]	4303	1			T77	10		T444	6		T435	1
values[37]	4063	1			T77	8		T444	5		T435	1
values[38]	4023	1			T77	7		T444	5		T435	1
values[39]	3899	1			T77	17		T444	5		T435	2
values[40]	3711	1			T77	5		T444	5		T435	3
values[41]	3544	1			T77	3		T444	5		T435	1
values[42]	3520	1			T77	4		T444	5		T435	1
values[43]	3454	1			T77	2		T444	5		T435	1
values[44]	3446	1			T77	7		T444	5		T435	2
values[45]	3294	1			T77	2		T444	5		T435	3
values[46]	3134	1			T77	1		T444	5		T435	1
values[47]	3147	1			T77	1		T444	5		T435	4
values[48]	3098	1			T77	2		T444	5		T435	2
values[49]	3042	1			T77	4		T444	5		T435	1
values[50]	2990	1			T77	1		T444	5		T435	2
values[51]	2891	1			T77	3		T444	7		T435	1
values[52]	2783	1			T77	3		T444	5		T435	2
values[53]	2750	1			T77	4		T444	5		T435	3
values[54]	2633	1			T77	1		T444	5		T677	14
values[55]	2696	1			T77	3		T444	5		T677	13
values[56]	2662	1			T77	4		T444	5		T677	13
values[57]	2574	1			T77	1		T444	5		T677	13
values[58]	2521	1			T77	10		T444	5		T677	13
values[59]	2486	1			T77	3		T444	5		T677	14
values[60]	2565	1			T444	5		T677	13		T551	13
values[61]	2834	1			T444	6		T677	13		T551	14
values[62]	4332	1			T444	5		T677	13		T551	14
values[63]	16992	1			T444	7		T677	152		T551	15
values[64]	231503	1			T444	850		T677	2447		T551	2514

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4668312	1			T153	171		T76	1255		T77	15341
values[2]	768247	1			T153	54		T76	392		T77	2652
values[3]	74201	1			T153	18		T76	105		T77	63
values[4]	13563	1			T153	1		T76	30		T77	3
values[5]	4968	1			T76	7		T79	1		T444	9
values[6]	2858	1			T76	4		T444	3		T677	5
values[7]	2127	1			T76	2		T677	1		T551	1
values[8]	1855	1			T76	1		T677	1		T459	6
values[9]	1728	1			T677	1		T459	5		T807	2
values[10]	1643	1			T677	1		T459	9		T807	2
values[11]	1406	1			T677	1		T459	11		T807	2
values[12]	1225	1			T677	1		T459	12		T807	2
values[13]	1178	1			T677	1		T459	15		T807	2
values[14]	1069	1			T677	1		T459	9		T807	2
values[15]	1065	1			T677	1		T459	6		T807	2
values[16]	959	1			T677	1		T459	5		T807	2
values[17]	875	1			T677	1		T459	5		T807	2
values[18]	792	1			T677	1		T459	2		T807	2
values[19]	711	1			T677	1		T459	2		T807	2
values[20]	730	1			T677	1		T459	2		T807	2
values[21]	637	1			T677	1		T459	2		T807	3
values[22]	731	1			T677	1		T459	4		T807	2
values[23]	723	1			T677	1		T459	5		T807	2
values[24]	668	1			T677	1		T459	7		T807	2
values[25]	609	1			T677	1		T459	3		T807	2
values[26]	614	1			T677	1		T459	7		T807	2
values[27]	599	1			T677	1		T459	8		T807	2
values[28]	613	1			T677	1		T459	5		T807	2
values[29]	564	1			T677	1		T459	8		T807	2
values[30]	572	1			T677	1		T459	3		T807	2
values[31]	590	1			T677	1		T459	4		T807	2
values[32]	563	1			T677	1		T459	2		T807	2
values[33]	518	1			T677	1		T459	2		T807	2
values[34]	517	1			T677	1		T459	3		T807	2
values[35]	534	1			T677	1		T459	5		T807	2
values[36]	492	1			T677	1		T459	5		T807	2
values[37]	475	1			T677	1		T459	3		T807	2
values[38]	460	1			T677	1		T459	9		T807	2
values[39]	517	1			T677	1		T459	4		T807	2
values[40]	482	1			T677	1		T459	3		T807	2
values[41]	431	1			T677	1		T459	4		T807	2
values[42]	451	1			T677	1		T459	2		T807	2
values[43]	441	1			T677	1		T459	6		T807	2
values[44]	428	1			T677	1		T459	4		T807	2
values[45]	401	1			T677	1		T459	6		T807	2
values[46]	411	1			T677	1		T459	4		T807	2
values[47]	429	1			T677	1		T459	5		T807	2
values[48]	415	1			T677	1		T459	7		T807	2
values[49]	386	1			T677	1		T459	4		T807	2
values[50]	401	1			T677	1		T459	3		T807	2
values[51]	386	1			T677	1		T459	4		T807	2
values[52]	353	1			T677	1		T459	3		T807	2
values[53]	358	1			T677	1		T459	6		T807	2
values[54]	334	1			T677	1		T459	7		T807	2
values[55]	344	1			T677	1		T459	10		T807	2
values[56]	346	1			T677	1		T459	3		T807	2
values[57]	367	1			T677	1		T459	5		T807	2
values[58]	359	1			T677	1		T459	6		T807	2
values[59]	318	1			T677	1		T459	3		T807	2
values[60]	356	1			T677	1		T459	5		T807	2
values[61]	390	1			T677	1		T459	2		T807	2
values[62]	674	1			T677	1		T459	10		T807	2
values[63]	3148	1			T677	1		T459	43		T807	2
values[64]	28445	1			T677	207		T459	101		T807	436

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	597646	1			T153	2		T76	16		T77	364
values[2]	2552569	1			T153	12		T76	1349		T77	11241
values[3]	1108786	1			T153	49		T76	420		T77	2073
values[4]	137900	1			T153	31		T76	30		T77	145
values[5]	70882	1			T153	23		T76	1		T77	107
values[6]	46740	1			T153	12		T76	1		T77	109
values[7]	34013	1			T153	24		T77	84		T444	5
values[8]	27334	1			T153	17		T77	51		T444	5
values[9]	23260	1			T153	11		T77	60		T444	5
values[10]	20950	1			T153	14		T77	50		T444	5
values[11]	18485	1			T153	6		T77	42		T444	5
values[12]	16406	1			T153	6		T77	48		T444	5
values[13]	15364	1			T153	3		T77	35		T444	5
values[14]	14773	1			T77	44		T444	5		T435	6
values[15]	13764	1			T77	43		T444	5		T435	11
values[16]	13358	1			T77	44		T444	5		T435	3
values[17]	13068	1			T77	44		T444	5		T435	1
values[18]	12382	1			T77	44		T444	5		T435	8
values[19]	11709	1			T77	41		T444	5		T435	5
values[20]	11486	1			T77	49		T444	5		T435	3
values[21]	11252	1			T77	51		T444	5		T435	9
values[22]	10765	1			T77	54		T444	5		T435	13
values[23]	10565	1			T77	40		T444	5		T435	9
values[24]	10080	1			T77	44		T444	5		T435	13
values[25]	9328	1			T77	35		T444	5		T435	15
values[26]	9063	1			T77	32		T444	5		T435	13
values[27]	8626	1			T77	47		T444	5		T435	5
values[28]	8152	1			T77	33		T444	5		T435	4
values[29]	7661	1			T77	29		T444	5		T435	9
values[30]	7004	1			T77	44		T444	5		T435	5
values[31]	6744	1			T77	20		T444	5		T435	3
values[32]	6291	1			T77	15		T444	6		T435	1
values[33]	5901	1			T77	17		T444	5		T435	1
values[34]	5392	1			T77	3		T444	5		T435	1
values[35]	5005	1			T77	2		T444	5		T435	5
values[36]	4847	1			T77	4		T444	5		T435	5
values[37]	4537	1			T77	5		T444	5		T435	7
values[38]	4150	1			T77	4		T444	5		T435	4
values[39]	3970	1			T77	5		T444	5		T677	13
values[40]	3861	1			T77	2		T444	5		T677	13
values[41]	3821	1			T77	5		T444	5		T677	13
values[42]	3576	1			T77	2		T444	5		T677	13
values[43]	3523	1			T444	5		T677	13		T551	13
values[44]	3494	1			T444	5		T677	13		T551	13
values[45]	3448	1			T444	5		T677	13		T551	13
values[46]	3394	1			T444	5		T677	13		T551	13
values[47]	3396	1			T444	5		T677	13		T551	13
values[48]	3394	1			T444	5		T677	13		T551	13
values[49]	3288	1			T444	5		T677	13		T551	13
values[50]	3226	1			T444	5		T677	13		T551	13
values[51]	3177	1			T444	5		T677	13		T551	13
values[52]	3057	1			T444	5		T677	13		T551	13
values[53]	3084	1			T444	5		T677	14		T551	13
values[54]	2990	1			T444	5		T677	13		T551	13
values[55]	2977	1			T444	5		T677	13		T551	13
values[56]	2964	1			T444	5		T677	14		T551	13
values[57]	2876	1			T444	5		T677	13		T551	13
values[58]	2864	1			T444	5		T677	14		T551	13
values[59]	2737	1			T444	5		T677	13		T551	13
values[60]	2722	1			T444	5		T677	13		T551	13
values[61]	2872	1			T444	5		T677	13		T551	13
values[62]	3908	1			T444	5		T677	13		T551	13
values[63]	19775	1			T444	45		T677	16		T551	277
values[64]	222434	1			T444	916		T677	2612		T551	2041