Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2450007	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33668429

1

T4

4520

T5

111219

T6

5612

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	24980554	1			T4	1573		T5	98495		T6	2375
values[0x0]	9357471	1			T4	2947		T5	12724		T6	3237
values[0x1]	1780411	1			T4	295		T5	4		T6	421

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	748072	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

35370364

1

T4

4815

T5

111223

T6

6033

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16720512	1			T4	2408		T5	55612		T6	3017
valid_sources[0x01]	16719342	1			T4	2407		T5	55611		T6	3016
valid_sources[0x02]	43398	1			T146	283		T546	14		T392	817
valid_sources[0x03]	43319	1			T32	2		T146	289		T546	9
valid_sources[0x04]	43925	1			T201	2		T146	309		T546	23
valid_sources[0x05]	43236	1			T201	2		T146	328		T546	23
valid_sources[0x06]	42700	1			T32	3		T68	2		T201	3
valid_sources[0x07]	43243	1			T201	2		T146	196		T546	24
valid_sources[0x08]	43455	1			T32	3		T146	303		T546	13
valid_sources[0x09]	42764	1			T32	1		T68	2		T201	1
valid_sources[0x0a]	42720	1			T201	1		T146	286		T546	11
valid_sources[0x0b]	45980	1			T32	1		T146	261		T546	25
valid_sources[0x0c]	42306	1			T32	2		T146	287		T546	14
valid_sources[0x0d]	43778	1			T32	1		T146	269		T546	15
valid_sources[0x0e]	43308	1			T146	314		T546	18		T392	843
valid_sources[0x0f]	43068	1			T32	1		T68	2		T146	307
valid_sources[0x10]	43105	1			T201	5		T146	241		T546	20
valid_sources[0x11]	42254	1			T32	1		T146	283		T546	20
valid_sources[0x12]	43318	1			T32	1		T200	39		T146	284
valid_sources[0x13]	42980	1			T32	1		T37	4		T146	310
valid_sources[0x14]	42611	1			T32	2		T68	2		T37	2
valid_sources[0x15]	42937	1			T32	3		T146	293		T546	6
valid_sources[0x16]	42620	1			T68	2		T146	296		T546	12
valid_sources[0x17]	43623	1			T68	2		T146	319		T546	21
valid_sources[0x18]	43012	1			T146	283		T546	18		T392	781
valid_sources[0x19]	43774	1			T146	324		T546	18		T392	781
valid_sources[0x1a]	42924	1			T68	9		T146	341		T546	24
valid_sources[0x1b]	42954	1			T32	1		T146	289		T546	14
valid_sources[0x1c]	42781	1			T201	1		T146	310		T546	19
valid_sources[0x1d]	43093	1			T32	2		T146	268		T546	10
valid_sources[0x1e]	42470	1			T201	2		T146	237		T546	25
valid_sources[0x1f]	42279	1			T146	286		T546	10		T392	805
valid_sources[0x20]	43019	1			T201	1		T146	236		T546	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24094711

1

T4

1573

T5

98495

T6

2375

values[0x0]

all_enables

biggest_size

9318890

1

T4

2947

T5

12724

T6

3237

values[0x1]

all_enables

biggest_size

254828

1

T32

18

T68

17

T37

17

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2892002	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

457538

1

T153

22

T76

271

T77

75

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1133758	1			T153	64		T76	630		T77	309
values[0x0]	1083682	1			T153	56		T76	643		T77	65
values[0x1]	1132100	1			T153	75		T76	585		T77	292

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2238706	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1110834

1

T153

59

T76

650

T77

252

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52347	1			T153	2		T76	33		T77	10
valid_sources[0x01]	52282	1			T76	17		T77	6		T79	22
valid_sources[0x02]	51537	1			T153	3		T76	31		T77	12
valid_sources[0x03]	52621	1			T76	34		T77	7		T79	44
valid_sources[0x04]	52443	1			T153	3		T76	29		T77	7
valid_sources[0x05]	51910	1			T153	4		T76	25		T77	10
valid_sources[0x06]	52813	1			T76	25		T77	11		T78	1
valid_sources[0x07]	52591	1			T153	4		T76	31		T77	5
valid_sources[0x08]	52557	1			T153	2		T76	25		T77	12
valid_sources[0x09]	51592	1			T153	4		T76	27		T77	10
valid_sources[0x0a]	52357	1			T153	3		T76	22		T77	12
valid_sources[0x0b]	51994	1			T153	3		T76	24		T77	7
valid_sources[0x0c]	52805	1			T76	26		T77	11		T78	1
valid_sources[0x0d]	52572	1			T153	4		T76	39		T77	9
valid_sources[0x0e]	53036	1			T153	5		T76	28		T77	11
valid_sources[0x0f]	52803	1			T153	5		T76	29		T77	5
valid_sources[0x10]	52040	1			T153	3		T76	24		T77	8
valid_sources[0x11]	51669	1			T153	3		T76	35		T77	13
valid_sources[0x12]	52005	1			T153	7		T76	24		T77	18
valid_sources[0x13]	52707	1			T153	11		T76	20		T77	15
valid_sources[0x14]	52820	1			T153	3		T76	33		T77	2
valid_sources[0x15]	52264	1			T76	18		T77	10		T79	19
valid_sources[0x16]	52959	1			T153	3		T76	30		T77	15
valid_sources[0x17]	52558	1			T153	3		T76	24		T77	15
valid_sources[0x18]	52191	1			T76	32		T77	12		T78	1
valid_sources[0x19]	51536	1			T153	5		T76	31		T77	19
valid_sources[0x1a]	52007	1			T76	36		T77	5		T79	30
valid_sources[0x1b]	52304	1			T153	6		T76	27		T77	13
valid_sources[0x1c]	52920	1			T153	5		T76	26		T77	9
valid_sources[0x1d]	52296	1			T153	2		T76	31		T77	7
valid_sources[0x1e]	52200	1			T153	4		T76	30		T77	12
valid_sources[0x1f]	51433	1			T153	1		T76	29		T77	7
valid_sources[0x20]	51915	1			T153	4		T76	38		T77	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48278

1

T153

1

T76

25

T77

28

values[0x0]

all_enables

biggest_size

361484

1

T153

17

T76

225

T77

28

values[0x1]

all_enables

biggest_size

47776

1

T153

4

T76

21

T77

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3090784	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

504602

1

T153

32

T76

250

T77

103

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1230639	1			T153	81		T76	614		T77	415
values[0x0]	1136614	1			T153	74		T76	554		T77	76
values[0x1]	1228133	1			T153	89		T76	628		T77	371

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2372919	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1222467

1

T153

80

T76

616

T77

328

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56115	1			T76	13		T77	6		T78	1
valid_sources[0x01]	56571	1			T153	1		T76	54		T77	7
valid_sources[0x02]	55767	1			T153	13		T76	39		T77	9
valid_sources[0x03]	56941	1			T153	1		T76	14		T77	12
valid_sources[0x04]	55935	1			T153	3		T76	27		T77	15
valid_sources[0x05]	56493	1			T76	17		T77	7		T78	1
valid_sources[0x06]	56921	1			T153	1		T76	19		T77	6
valid_sources[0x07]	57094	1			T76	43		T77	6		T78	4
valid_sources[0x08]	56596	1			T153	1		T76	46		T77	6
valid_sources[0x09]	56426	1			T153	5		T76	56		T77	14
valid_sources[0x0a]	56526	1			T153	4		T76	22		T77	20
valid_sources[0x0b]	56036	1			T153	6		T76	41		T77	12
valid_sources[0x0c]	55919	1			T76	14		T77	22		T78	3
valid_sources[0x0d]	55837	1			T76	29		T77	15		T78	3
valid_sources[0x0e]	57566	1			T76	29		T77	15		T78	2
valid_sources[0x0f]	56047	1			T76	23		T77	11		T78	1
valid_sources[0x10]	56325	1			T153	6		T76	19		T77	12
valid_sources[0x11]	56096	1			T76	22		T77	13		T78	2
valid_sources[0x12]	55857	1			T153	4		T76	12		T77	18
valid_sources[0x13]	56416	1			T76	52		T77	17		T78	3
valid_sources[0x14]	56793	1			T153	29		T76	8		T77	11
valid_sources[0x15]	55064	1			T153	10		T76	37		T77	10
valid_sources[0x16]	55831	1			T153	2		T76	43		T77	4
valid_sources[0x17]	55465	1			T153	10		T76	52		T77	15
valid_sources[0x18]	55942	1			T153	1		T76	17		T77	5
valid_sources[0x19]	56708	1			T153	10		T76	46		T77	13
valid_sources[0x1a]	56140	1			T153	2		T76	39		T77	12
valid_sources[0x1b]	56529	1			T153	6		T76	7		T77	14
valid_sources[0x1c]	56216	1			T153	2		T76	43		T77	5
valid_sources[0x1d]	55271	1			T153	5		T76	19		T77	19
valid_sources[0x1e]	56677	1			T76	39		T77	23		T78	7
valid_sources[0x1f]	56375	1			T76	24		T77	18		T78	2
valid_sources[0x20]	55577	1			T153	11		T76	27		T77	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52772

1

T153

1

T76

31

T77

41

values[0x0]

all_enables

biggest_size

399471

1

T153

22

T76

203

T77

29

values[0x1]

all_enables

biggest_size

52359

1

T153

9

T76

16

T77

33

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2916218	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

461724

1

T153

39

T76

254

T77

81

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1141619	1			T153	63		T76	627		T77	330
values[0x0]	1093911	1			T153	75		T76	577		T77	65
values[0x1]	1142412	1			T153	72		T76	613		T77	287

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2258833	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1119109

1

T153

74

T76

602

T77

282

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53076	1			T153	3		T76	48		T77	6
valid_sources[0x01]	52486	1			T153	3		T76	27		T77	7
valid_sources[0x02]	52332	1			T153	1		T76	24		T77	16
valid_sources[0x03]	52726	1			T153	4		T76	30		T77	11
valid_sources[0x04]	52788	1			T153	5		T76	27		T77	11
valid_sources[0x05]	53226	1			T153	1		T76	24		T77	11
valid_sources[0x06]	52221	1			T153	4		T76	19		T77	11
valid_sources[0x07]	52886	1			T153	3		T76	33		T77	1
valid_sources[0x08]	52157	1			T76	33		T77	8		T79	31
valid_sources[0x09]	52246	1			T153	4		T76	19		T77	9
valid_sources[0x0a]	52521	1			T153	1		T76	33		T77	13
valid_sources[0x0b]	52252	1			T153	6		T76	26		T77	9
valid_sources[0x0c]	52973	1			T153	6		T76	29		T77	14
valid_sources[0x0d]	51459	1			T153	4		T76	35		T77	15
valid_sources[0x0e]	53526	1			T153	3		T76	38		T77	22
valid_sources[0x0f]	53142	1			T153	3		T76	36		T77	8
valid_sources[0x10]	52903	1			T153	2		T76	35		T77	13
valid_sources[0x11]	51932	1			T153	4		T76	33		T77	11
valid_sources[0x12]	52688	1			T76	33		T77	11		T79	20
valid_sources[0x13]	53585	1			T153	3		T76	31		T77	14
valid_sources[0x14]	52689	1			T153	4		T76	20		T77	14
valid_sources[0x15]	52552	1			T153	3		T76	31		T77	8
valid_sources[0x16]	52521	1			T153	4		T76	18		T77	14
valid_sources[0x17]	53079	1			T153	5		T76	27		T77	9
valid_sources[0x18]	52348	1			T153	3		T76	20		T77	8
valid_sources[0x19]	52491	1			T153	4		T76	25		T77	8
valid_sources[0x1a]	53385	1			T153	3		T76	30		T77	19
valid_sources[0x1b]	53043	1			T153	5		T76	24		T77	12
valid_sources[0x1c]	54085	1			T153	6		T76	27		T77	4
valid_sources[0x1d]	52255	1			T153	6		T76	25		T77	9
valid_sources[0x1e]	53079	1			T153	6		T76	24		T77	13
valid_sources[0x1f]	52173	1			T153	5		T76	28		T77	7
valid_sources[0x20]	53098	1			T153	1		T76	23		T77	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48113

1

T153

7

T76

23

T77

25

values[0x0]

all_enables

biggest_size

365192

1

T153

29

T76

212

T77

31

values[0x1]

all_enables

biggest_size

48419

1

T153

3

T76

19

T77

25