Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473285817	51630474	0	0
DepthKnown_A	473285817	473181043	0	0
RvalidKnown_A	473285817	473181043	0	0
WreadyKnown_A	473285817	473181043	0	0
gen_passthru_fifo.paramCheckPass	984	984	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473285817	51630474	0	0
T4	74175	8415	0	0
T5	122840	137860	0	0
T6	90702	9780	0	0
T18	264854	33330	0	0
T19	343223	33155	0	0
T20	206643	13968	0	0
T46	267756	34076	0	0
T47	235511	29608	0	0
T63	134515	23030	0	0
T84	216478	29089	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473285817	473181043	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473285817	473181043	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473285817	473181043	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	984	984	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T63	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473285817	40813581	0	0
DepthKnown_A	473285817	473181043	0	0
RvalidKnown_A	473285817	473181043	0	0
WreadyKnown_A	473285817	473181043	0	0
gen_passthru_fifo.paramCheckPass	984	984	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473285817	40813581	0	0
T4	74175	6089	0	0
T5	122840	119265	0	0
T6	90702	7958	0	0
T18	264854	24469	0	0
T19	343223	28619	0	0
T20	206643	10542	0	0
T46	267756	25100	0	0
T47	235511	20722	0	0
T63	134515	15349	0	0
T84	216478	24864	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473285817	473181043	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473285817	473181043	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473285817	473181043	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	984	984	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T63	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473285817	38836491	0	0
DepthKnown_A	473285817	473181043	0	0
RvalidKnown_A	473285817	473181043	0	0
WreadyKnown_A	473285817	473181043	0	0
gen_passthru_fifo.paramCheckPass	984	984	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473285817	38836491	0	0
T4	74175	5003	0	0
T5	122840	171027	0	0
T6	90702	6148	0	0
T18	264854	18035	0	0
T19	343223	30847	0	0
T20	206643	5763	0	0
T46	267756	18422	0	0
T47	235511	15300	0	0
T63	134515	7092	0	0
T84	216478	11653	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473285817	473181043	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473285817	473181043	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473285817	473181043	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	984	984	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T63	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473285817	33437822	0	0
DepthKnown_A	473285817	473181043	0	0
RvalidKnown_A	473285817	473181043	0	0
WreadyKnown_A	473285817	473181043	0	0
gen_passthru_fifo.paramCheckPass	984	984	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473285817	33437822	0	0
T4	74175	4815	0	0
T5	122840	111223	0	0
T6	90702	6033	0	0
T18	264854	17648	0	0
T19	343223	30516	0	0
T20	206643	5593	0	0
T46	267756	18031	0	0
T47	235511	14909	0	0
T63	134515	6813	0	0
T84	216478	11392	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473285817	473181043	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473285817	473181043	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473285817	473181043	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	984	984	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T63	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	563920815	88357	0	0
DepthKnown_A	563920815	563804464	0	0
RvalidKnown_A	563920815	563804464	0	0
WreadyKnown_A	563920815	563804464	0	0
gen_passthru_fifo.paramCheckPass	2875	2875	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	88357	0	0
T4	74175	14	0	0
T5	122840	34	0	0
T6	90702	13	0	0
T18	264854	151	0	0
T19	343223	23	0	0
T20	206643	25	0	0
T46	267756	151	0	0
T47	235511	153	0	0
T63	134515	26	0	0
T84	216478	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2875	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T63	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	563920815	91178	0	0
DepthKnown_A	563920815	563804464	0	0
RvalidKnown_A	563920815	563804464	0	0
WreadyKnown_A	563920815	563804464	0	0
gen_passthru_fifo.paramCheckPass	2875	2875	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	91178	0	0
T4	74175	14	0	0
T5	122840	34	0	0
T6	90702	13	0	0
T18	264854	151	0	0
T19	343223	23	0	0
T20	206643	25	0	0
T46	267756	151	0	0
T47	235511	153	0	0
T63	134515	26	0	0
T84	216478	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2875	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T63	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	563920815	49986	0	0
DepthKnown_A	563920815	563804464	0	0
RvalidKnown_A	563920815	563804464	0	0
WreadyKnown_A	563920815	563804464	0	0
gen_passthru_fifo.paramCheckPass	2875	2875	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	49986	0	0
T4	74175	13	0	0
T5	122840	5	0	0
T6	90702	12	0	0
T18	264854	95	0	0
T19	343223	20	0	0
T20	206643	22	0	0
T46	267756	95	0	0
T47	235511	95	0	0
T63	134515	23	0	0
T84	216478	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2875	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T63	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	563920815	49986	0	0
DepthKnown_A	563920815	563804464	0	0
RvalidKnown_A	563920815	563804464	0	0
WreadyKnown_A	563920815	563804464	0	0
gen_passthru_fifo.paramCheckPass	2875	2875	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	49986	0	0
T4	74175	13	0	0
T5	122840	5	0	0
T6	90702	12	0	0
T18	264854	95	0	0
T19	343223	20	0	0
T20	206643	22	0	0
T46	267756	95	0	0
T47	235511	95	0	0
T63	134515	23	0	0
T84	216478	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2875	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T63	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	563920815	38371	0	0
DepthKnown_A	563920815	563804464	0	0
RvalidKnown_A	563920815	563804464	0	0
WreadyKnown_A	563920815	563804464	0	0
gen_passthru_fifo.paramCheckPass	2875	2875	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	38371	0	0
T4	74175	1	0	0
T5	122840	29	0	0
T6	90702	1	0	0
T18	264854	56	0	0
T19	343223	3	0	0
T20	206643	3	0	0
T46	267756	56	0	0
T47	235511	58	0	0
T63	134515	3	0	0
T84	216478	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2875	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T63	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	563920815	41192	0	0
DepthKnown_A	563920815	563804464	0	0
RvalidKnown_A	563920815	563804464	0	0
WreadyKnown_A	563920815	563804464	0	0
gen_passthru_fifo.paramCheckPass	2875	2875	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	41192	0	0
T4	74175	1	0	0
T5	122840	29	0	0
T6	90702	1	0	0
T18	264854	56	0	0
T19	343223	3	0	0
T20	206643	3	0	0
T46	267756	56	0	0
T47	235511	58	0	0
T63	134515	3	0	0
T84	216478	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563920815	563804464	0	0
T4	74175	74117	0	0
T5	122840	122835	0	0
T6	90702	90640	0	0
T18	264854	264738	0	0
T19	343223	343168	0	0
T20	206643	206581	0	0
T46	267756	267650	0	0
T47	235511	235405	0	0
T63	134515	134453	0	0
T84	216478	216416	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2875	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T63	1	1	0	0
T84	1	1	0	0