Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1490800	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32340749

1

T4

7165

T5

5480

T6

6037

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	23232858	1			T4	3158		T5	2191		T6	2360
values[0x0]	9107016	1			T4	4007		T5	3289		T6	3677
values[0x1]	1491675	1			T4	323		T5	307		T6	302

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10740	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

33820809

1

T4

7488

T5

5787

T6

6339

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16899553	1			T4	3744		T5	2894		T6	3170
valid_sources[0x01]	16898615	1			T4	3744		T5	2893		T6	3169
valid_sources[0x02]	593	1			T66	1		T40	57		T41	59
valid_sources[0x03]	575	1			T65	2		T40	49		T41	100
valid_sources[0x04]	482	1			T40	48		T41	38		T42	64
valid_sources[0x05]	535	1			T64	2		T167	1		T40	50
valid_sources[0x06]	567	1			T64	2		T167	1		T40	49
valid_sources[0x07]	482	1			T66	3		T9	1		T154	2
valid_sources[0x08]	445	1			T66	1		T167	2		T154	1
valid_sources[0x09]	568	1			T64	1		T40	50		T41	87
valid_sources[0x0a]	511	1			T64	1		T154	1		T40	45
valid_sources[0x0b]	553	1			T167	1		T40	54		T41	14
valid_sources[0x0c]	558	1			T64	1		T167	1		T40	62
valid_sources[0x0d]	481	1			T40	52		T41	48		T42	43
valid_sources[0x0e]	488	1			T167	1		T154	2		T40	64
valid_sources[0x0f]	565	1			T64	1		T65	1		T154	2
valid_sources[0x10]	483	1			T167	3		T40	40		T41	38
valid_sources[0x11]	562	1			T64	1		T66	3		T40	41
valid_sources[0x12]	548	1			T64	2		T40	53		T41	64
valid_sources[0x13]	463	1			T64	2		T167	1		T40	43
valid_sources[0x14]	593	1			T9	4		T167	1		T40	54
valid_sources[0x15]	620	1			T64	1		T65	3		T9	1
valid_sources[0x16]	498	1			T65	1		T66	1		T9	2
valid_sources[0x17]	563	1			T64	1		T65	1		T9	2
valid_sources[0x18]	554	1			T64	1		T154	1		T40	39
valid_sources[0x19]	539	1			T65	1		T9	10		T167	3
valid_sources[0x1a]	569	1			T66	3		T167	1		T40	48
valid_sources[0x1b]	522	1			T65	2		T66	3		T9	2
valid_sources[0x1c]	617	1			T40	49		T41	61		T42	85
valid_sources[0x1d]	542	1			T64	1		T154	1		T40	56
valid_sources[0x1e]	498	1			T40	51		T41	54		T42	46
valid_sources[0x1f]	482	1			T64	1		T167	2		T154	1
valid_sources[0x20]	521	1			T65	1		T167	1		T154	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23232858

1

T4

3158

T5

2191

T6

2360

values[0x0]

all_enables

biggest_size

9101564

1

T4

4007

T5

3289

T6

3677

values[0x1]

all_enables

biggest_size

6327

1

T64

10

T65

21

T66

18