Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484059368	51417494	0	0
DepthKnown_A	484059368	483954902	0	0
RvalidKnown_A	484059368	483954902	0	0
WreadyKnown_A	484059368	483954902	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	51417494	0	0
T4	140224	23963	0	0
T5	84690	10244	0	0
T6	100784	16251	0	0
T17	104156	13515	0	0
T18	260781	33372	0	0
T19	991451	304019	0	0
T43	500350	70343	0	0
T44	288369	36501	0	0
T57	207417	218139	0	0
T117	81945	8390	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484059368	40856893	0	0
DepthKnown_A	484059368	483954902	0	0
RvalidKnown_A	484059368	483954902	0	0
WreadyKnown_A	484059368	483954902	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	40856893	0	0
T4	140224	16286	0	0
T5	84690	7700	0	0
T6	100784	10640	0	0
T17	104156	10285	0	0
T18	260781	24253	0	0
T19	991451	152943	0	0
T43	500350	63421	0	0
T44	288369	27618	0	0
T57	207417	199879	0	0
T117	81945	6707	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484059368	39153680	0	0
DepthKnown_A	484059368	483954902	0	0
RvalidKnown_A	484059368	483954902	0	0
WreadyKnown_A	484059368	483954902	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	39153680	0	0
T4	140224	7761	0	0
T5	84690	5919	0	0
T6	100784	6527	0	0
T17	104156	6780	0	0
T18	260781	17768	0	0
T19	991451	28431	0	0
T43	500350	59734	0	0
T44	288369	20320	0	0
T57	207417	273975	0	0
T117	81945	5292	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484059368	33863226	0	0
DepthKnown_A	484059368	483954902	0	0
RvalidKnown_A	484059368	483954902	0	0
WreadyKnown_A	484059368	483954902	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	33863226	0	0
T4	140224	7488	0	0
T5	84690	5787	0	0
T6	100784	6339	0	0
T17	104156	6633	0	0
T18	260781	17376	0	0
T19	991451	26739	0	0
T43	500350	59332	0	0
T44	288369	19931	0	0
T57	207417	198148	0	0
T117	81945	5181	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484059368	64343	0	0
DepthKnown_A	484059368	483954902	0	0
RvalidKnown_A	484059368	483954902	0	0
WreadyKnown_A	484059368	483954902	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	64343	0	0
T4	140224	26	0	0
T5	84690	15	0	0
T6	100784	17	0	0
T17	104156	16	0	0
T18	260781	151	0	0
T19	991451	152	0	0
T43	500350	39	0	0
T44	288369	151	0	0
T57	207417	56	0	0
T117	81945	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484059368	64343	0	0
DepthKnown_A	484059368	483954902	0	0
RvalidKnown_A	484059368	483954902	0	0
WreadyKnown_A	484059368	483954902	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	64343	0	0
T4	140224	26	0	0
T5	84690	15	0	0
T6	100784	17	0	0
T17	104156	16	0	0
T18	260781	151	0	0
T19	991451	152	0	0
T43	500350	39	0	0
T44	288369	151	0	0
T57	207417	56	0	0
T117	81945	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484059368	50701	0	0
DepthKnown_A	484059368	483954902	0	0
RvalidKnown_A	484059368	483954902	0	0
WreadyKnown_A	484059368	483954902	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	50701	0	0
T4	140224	23	0	0
T5	84690	14	0	0
T6	100784	12	0	0
T17	104156	13	0	0
T18	260781	95	0	0
T19	991451	143	0	0
T43	500350	37	0	0
T44	288369	95	0	0
T57	207417	5	0	0
T117	81945	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484059368	50701	0	0
DepthKnown_A	484059368	483954902	0	0
RvalidKnown_A	484059368	483954902	0	0
WreadyKnown_A	484059368	483954902	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	50701	0	0
T4	140224	23	0	0
T5	84690	14	0	0
T6	100784	12	0	0
T17	104156	13	0	0
T18	260781	95	0	0
T19	991451	143	0	0
T43	500350	37	0	0
T44	288369	95	0	0
T57	207417	5	0	0
T117	81945	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484059368	13642	0	0
DepthKnown_A	484059368	483954902	0	0
RvalidKnown_A	484059368	483954902	0	0
WreadyKnown_A	484059368	483954902	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	13642	0	0
T4	140224	3	0	0
T5	84690	1	0	0
T6	100784	5	0	0
T17	104156	3	0	0
T18	260781	56	0	0
T19	991451	9	0	0
T43	500350	2	0	0
T44	288369	56	0	0
T57	207417	51	0	0
T117	81945	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484059368	13642	0	0
DepthKnown_A	484059368	483954902	0	0
RvalidKnown_A	484059368	483954902	0	0
WreadyKnown_A	484059368	483954902	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	13642	0	0
T4	140224	3	0	0
T5	84690	1	0	0
T6	100784	5	0	0
T17	104156	3	0	0
T18	260781	56	0	0
T19	991451	9	0	0
T43	500350	2	0	0
T44	288369	56	0	0
T57	207417	51	0	0
T117	81945	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	483954902	0	0
T4	140224	140173	0	0
T5	84690	84639	0	0
T6	100784	100722	0	0
T17	104156	104105	0	0
T18	260781	260672	0	0
T19	991451	990498	0	0
T43	500350	500237	0	0
T44	288369	288260	0	0
T57	207417	207411	0	0
T117	81945	81887	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0