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Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_111.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.90 85.71 100.00 60.00 u_ip_3_p_111


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_112.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.90 85.71 100.00 60.00 u_ip_3_p_112


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_113.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.90 85.71 100.00 60.00 u_ip_3_p_113


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_114.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.90 85.71 100.00 60.00 u_ip_3_p_114


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_115.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.90 85.71 100.00 60.00 u_ip_3_p_115


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_116.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.90 85.71 100.00 60.00 u_ip_3_p_116


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_117.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.90 85.71 100.00 60.00 u_ip_3_p_117


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_118.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.90 85.71 100.00 60.00 u_ip_3_p_118


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_119.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.90 85.71 100.00 60.00 u_ip_3_p_119


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_120.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.90 85.71 100.00 60.00 u_ip_3_p_120


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_121.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.90 85.71 100.00 60.00 u_ip_3_p_121


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_122.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.90 85.71 100.00 60.00 u_ip_3_p_122


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_123.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.90 85.71 100.00 60.00 u_ip_3_p_123


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_111.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_112.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_113.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_114.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_115.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_116.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_117.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_118.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_119.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_120.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_121.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_122.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_123.wr_en_data_arb
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_111.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_112.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_113.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_114.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_115.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_116.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_117.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_118.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_119.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_120.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_121.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_122.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_3_p_123.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

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