Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.12 90.71 80.62 90.04 92.03 96.47 84.87


Total test records in report: 988
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T70 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.450821246 Jun 04 03:26:09 PM PDT 24 Jun 04 03:31:03 PM PDT 24 3257915123 ps
T572 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1185958860 Jun 04 03:42:16 PM PDT 24 Jun 04 03:52:01 PM PDT 24 4104958584 ps
T329 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1243823836 Jun 04 03:15:51 PM PDT 24 Jun 04 03:40:29 PM PDT 24 6892428032 ps
T328 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2848388092 Jun 04 03:24:56 PM PDT 24 Jun 04 04:27:46 PM PDT 24 15947663872 ps
T331 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2363925142 Jun 04 03:28:59 PM PDT 24 Jun 04 03:49:28 PM PDT 24 7667507102 ps
T363 /workspace/coverage/default/0.chip_sw_aon_timer_irq.2751988122 Jun 04 03:14:52 PM PDT 24 Jun 04 03:20:07 PM PDT 24 3233387556 ps
T573 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.2172074500 Jun 04 03:13:29 PM PDT 24 Jun 04 03:17:17 PM PDT 24 3282017090 ps
T531 /workspace/coverage/default/9.chip_sw_all_escalation_resets.3108899041 Jun 04 03:45:23 PM PDT 24 Jun 04 03:57:09 PM PDT 24 5687324320 ps
T574 /workspace/coverage/default/1.chip_tap_straps_prod.3583476324 Jun 04 03:27:34 PM PDT 24 Jun 04 03:29:46 PM PDT 24 2330905461 ps
T575 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.840436592 Jun 04 03:19:49 PM PDT 24 Jun 04 04:05:58 PM PDT 24 11530319680 ps
T576 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3658644129 Jun 04 03:19:27 PM PDT 24 Jun 04 03:30:16 PM PDT 24 4555098362 ps
T577 /workspace/coverage/default/1.chip_sw_edn_kat.3577129969 Jun 04 03:25:28 PM PDT 24 Jun 04 03:34:49 PM PDT 24 3262681600 ps
T278 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.760446955 Jun 04 03:17:29 PM PDT 24 Jun 04 03:28:34 PM PDT 24 5869305036 ps
T280 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2721577746 Jun 04 03:26:09 PM PDT 24 Jun 04 04:10:47 PM PDT 24 29661842507 ps
T281 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2817052716 Jun 04 03:13:12 PM PDT 24 Jun 04 04:17:03 PM PDT 24 17467937192 ps
T282 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3322690321 Jun 04 03:45:25 PM PDT 24 Jun 04 04:23:37 PM PDT 24 12803147396 ps
T283 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1528450902 Jun 04 03:45:30 PM PDT 24 Jun 04 03:52:13 PM PDT 24 4012929864 ps
T107 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.341713010 Jun 04 03:36:49 PM PDT 24 Jun 04 03:45:58 PM PDT 24 4834714348 ps
T284 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2843758986 Jun 04 03:22:29 PM PDT 24 Jun 04 03:25:45 PM PDT 24 2738377229 ps
T285 /workspace/coverage/default/0.chip_sw_aes_smoketest.4035286043 Jun 04 03:17:16 PM PDT 24 Jun 04 03:21:19 PM PDT 24 3397451724 ps
T286 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3273926366 Jun 04 03:43:07 PM PDT 24 Jun 04 04:00:21 PM PDT 24 9544081752 ps
T230 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2794181849 Jun 04 03:12:38 PM PDT 24 Jun 04 03:18:22 PM PDT 24 2793198661 ps
T578 /workspace/coverage/default/0.rom_keymgr_functest.3420144745 Jun 04 03:17:29 PM PDT 24 Jun 04 03:29:15 PM PDT 24 4625320976 ps
T441 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2101959914 Jun 04 03:46:25 PM PDT 24 Jun 04 03:52:15 PM PDT 24 3884173944 ps
T485 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3401758735 Jun 04 03:51:04 PM PDT 24 Jun 04 03:56:31 PM PDT 24 3363616118 ps
T579 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.510775963 Jun 04 03:45:10 PM PDT 24 Jun 04 04:05:08 PM PDT 24 10223555133 ps
T148 /workspace/coverage/default/1.chip_sw_kmac_app_rom.3152720342 Jun 04 03:26:00 PM PDT 24 Jun 04 03:30:12 PM PDT 24 2401581640 ps
T310 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.203027422 Jun 04 03:41:44 PM PDT 24 Jun 04 03:53:05 PM PDT 24 4371014880 ps
T381 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3415545044 Jun 04 03:14:41 PM PDT 24 Jun 04 03:21:50 PM PDT 24 5180131936 ps
T330 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1951724884 Jun 04 03:26:15 PM PDT 24 Jun 04 03:36:44 PM PDT 24 5520116160 ps
T580 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2281459085 Jun 04 03:14:42 PM PDT 24 Jun 04 03:48:46 PM PDT 24 21529215154 ps
T38 /workspace/coverage/default/0.chip_sw_gpio.1478364645 Jun 04 03:14:20 PM PDT 24 Jun 04 03:21:15 PM PDT 24 3663241726 ps
T378 /workspace/coverage/default/89.chip_sw_all_escalation_resets.3940480399 Jun 04 03:52:17 PM PDT 24 Jun 04 04:02:53 PM PDT 24 5037349450 ps
T581 /workspace/coverage/default/2.chip_sw_edn_sw_mode.1453687716 Jun 04 03:35:48 PM PDT 24 Jun 04 04:00:37 PM PDT 24 7264858400 ps
T338 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.147252542 Jun 04 03:21:32 PM PDT 24 Jun 04 03:25:50 PM PDT 24 3557352936 ps
T582 /workspace/coverage/default/2.chip_sw_aes_enc.1214132219 Jun 04 03:34:43 PM PDT 24 Jun 04 03:39:10 PM PDT 24 3086084038 ps
T583 /workspace/coverage/default/2.chip_sw_csrng_smoketest.1895167959 Jun 04 03:45:23 PM PDT 24 Jun 04 03:49:12 PM PDT 24 2469598758 ps
T584 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1394066709 Jun 04 03:14:02 PM PDT 24 Jun 04 03:32:19 PM PDT 24 6709704404 ps
T26 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2653148300 Jun 04 03:18:44 PM PDT 24 Jun 04 03:25:30 PM PDT 24 5206656962 ps
T585 /workspace/coverage/default/0.chip_sw_csrng_smoketest.3410943960 Jun 04 03:18:18 PM PDT 24 Jun 04 03:21:53 PM PDT 24 3445887396 ps
T586 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.481623010 Jun 04 03:34:12 PM PDT 24 Jun 04 03:42:04 PM PDT 24 6108394708 ps
T587 /workspace/coverage/default/2.chip_sw_otbn_randomness.3142890280 Jun 04 03:35:49 PM PDT 24 Jun 04 03:52:12 PM PDT 24 5722342480 ps
T13 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.3130550750 Jun 04 03:31:03 PM PDT 24 Jun 04 03:35:47 PM PDT 24 3767102920 ps
T588 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2077605629 Jun 04 03:25:37 PM PDT 24 Jun 04 03:31:49 PM PDT 24 2706929980 ps
T589 /workspace/coverage/default/1.chip_sw_example_concurrency.3650292251 Jun 04 03:17:55 PM PDT 24 Jun 04 03:24:06 PM PDT 24 3432303690 ps
T590 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.4191106725 Jun 04 03:35:24 PM PDT 24 Jun 04 03:48:54 PM PDT 24 7857592198 ps
T591 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2801537277 Jun 04 03:35:32 PM PDT 24 Jun 04 04:41:23 PM PDT 24 17749422780 ps
T384 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3997278551 Jun 04 03:49:56 PM PDT 24 Jun 04 03:56:42 PM PDT 24 4480497048 ps
T386 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3030406145 Jun 04 03:37:24 PM PDT 24 Jun 04 03:47:28 PM PDT 24 7268450558 ps
T231 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1762112959 Jun 04 03:23:22 PM PDT 24 Jun 04 03:36:00 PM PDT 24 5044170842 ps
T36 /workspace/coverage/default/0.chip_sw_usbdev_dpi.1202044065 Jun 04 03:14:14 PM PDT 24 Jun 04 04:03:39 PM PDT 24 12219578288 ps
T203 /workspace/coverage/default/1.chip_plic_all_irqs_20.59351043 Jun 04 03:27:10 PM PDT 24 Jun 04 03:39:11 PM PDT 24 3939745508 ps
T387 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.120328698 Jun 04 03:47:09 PM PDT 24 Jun 04 03:52:46 PM PDT 24 3401764370 ps
T388 /workspace/coverage/default/2.chip_sw_kmac_idle.903705808 Jun 04 03:36:03 PM PDT 24 Jun 04 03:40:28 PM PDT 24 2904352644 ps
T389 /workspace/coverage/default/0.chip_sw_example_rom.1039187024 Jun 04 03:13:00 PM PDT 24 Jun 04 03:14:44 PM PDT 24 1982685016 ps
T207 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3412606711 Jun 04 03:14:12 PM PDT 24 Jun 04 03:22:32 PM PDT 24 3827919646 ps
T192 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.628315853 Jun 04 03:27:50 PM PDT 24 Jun 04 03:33:33 PM PDT 24 2702664536 ps
T211 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3153321987 Jun 04 03:31:38 PM PDT 24 Jun 04 03:45:10 PM PDT 24 4426947780 ps
T592 /workspace/coverage/default/2.chip_sw_kmac_entropy.3425858333 Jun 04 03:31:15 PM PDT 24 Jun 04 03:36:17 PM PDT 24 2446442200 ps
T593 /workspace/coverage/default/2.chip_sw_example_rom.3419709533 Jun 04 03:30:25 PM PDT 24 Jun 04 03:32:30 PM PDT 24 2388961544 ps
T594 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3357732259 Jun 04 03:22:31 PM PDT 24 Jun 04 04:11:09 PM PDT 24 30548249842 ps
T458 /workspace/coverage/default/3.chip_sw_all_escalation_resets.1613014686 Jun 04 03:40:39 PM PDT 24 Jun 04 03:51:14 PM PDT 24 5233566238 ps
T595 /workspace/coverage/default/2.chip_sw_flash_crash_alert.4047012883 Jun 04 03:38:16 PM PDT 24 Jun 04 03:49:56 PM PDT 24 5276793300 ps
T596 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.4278723670 Jun 04 03:32:12 PM PDT 24 Jun 04 03:49:39 PM PDT 24 5318953596 ps
T597 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.4273994674 Jun 04 03:34:35 PM PDT 24 Jun 04 03:39:22 PM PDT 24 2834808612 ps
T598 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3154703686 Jun 04 03:37:30 PM PDT 24 Jun 04 04:20:45 PM PDT 24 28758065456 ps
T599 /workspace/coverage/default/1.chip_tap_straps_dev.1647263464 Jun 04 03:27:42 PM PDT 24 Jun 04 03:29:55 PM PDT 24 2817458899 ps
T199 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3937625527 Jun 04 03:48:19 PM PDT 24 Jun 04 03:55:18 PM PDT 24 3727743440 ps
T600 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3646643565 Jun 04 03:36:03 PM PDT 24 Jun 04 03:59:24 PM PDT 24 7884768868 ps
T601 /workspace/coverage/default/2.chip_sw_aes_masking_off.2822188427 Jun 04 03:34:52 PM PDT 24 Jun 04 03:40:33 PM PDT 24 2981874068 ps
T602 /workspace/coverage/default/1.chip_sw_otbn_randomness.917952793 Jun 04 03:22:35 PM PDT 24 Jun 04 03:40:36 PM PDT 24 6295649400 ps
T603 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1017744287 Jun 04 03:14:11 PM PDT 24 Jun 04 03:32:15 PM PDT 24 5845358600 ps
T261 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1808543618 Jun 04 03:41:50 PM PDT 24 Jun 04 03:45:26 PM PDT 24 2690079400 ps
T478 /workspace/coverage/default/93.chip_sw_all_escalation_resets.1797101626 Jun 04 03:52:26 PM PDT 24 Jun 04 04:00:47 PM PDT 24 5099802912 ps
T446 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.867511474 Jun 04 03:48:04 PM PDT 24 Jun 04 03:54:23 PM PDT 24 3886915416 ps
T604 /workspace/coverage/default/0.chip_sw_hmac_multistream.2959286638 Jun 04 03:16:03 PM PDT 24 Jun 04 03:39:05 PM PDT 24 7179145054 ps
T472 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3220888333 Jun 04 03:53:24 PM PDT 24 Jun 04 03:59:45 PM PDT 24 3222836504 ps
T250 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2116985786 Jun 04 03:21:11 PM PDT 24 Jun 04 03:30:05 PM PDT 24 6197860872 ps
T605 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1849609060 Jun 04 03:16:00 PM PDT 24 Jun 04 03:51:03 PM PDT 24 12105228541 ps
T212 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.273908534 Jun 04 03:32:31 PM PDT 24 Jun 04 03:48:07 PM PDT 24 5272277014 ps
T11 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3104553307 Jun 04 03:18:34 PM PDT 24 Jun 04 03:22:45 PM PDT 24 3200233282 ps
T414 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4004331272 Jun 04 03:16:13 PM PDT 24 Jun 04 03:26:37 PM PDT 24 5545471136 ps
T415 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3336429512 Jun 04 03:21:28 PM PDT 24 Jun 04 04:16:05 PM PDT 24 14479857976 ps
T416 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3676289089 Jun 04 03:34:52 PM PDT 24 Jun 04 04:01:10 PM PDT 24 7798479176 ps
T417 /workspace/coverage/default/27.chip_sw_all_escalation_resets.1214749281 Jun 04 03:46:35 PM PDT 24 Jun 04 04:00:49 PM PDT 24 5788963120 ps
T204 /workspace/coverage/default/0.chip_plic_all_irqs_20.2368816664 Jun 04 03:14:49 PM PDT 24 Jun 04 03:26:05 PM PDT 24 4574119288 ps
T418 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3554870013 Jun 04 03:20:47 PM PDT 24 Jun 04 03:31:37 PM PDT 24 4276941496 ps
T419 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3403912260 Jun 04 03:30:15 PM PDT 24 Jun 04 03:39:00 PM PDT 24 5828330740 ps
T253 /workspace/coverage/default/34.chip_sw_all_escalation_resets.2439332869 Jun 04 03:47:00 PM PDT 24 Jun 04 03:57:19 PM PDT 24 4596121340 ps
T375 /workspace/coverage/default/62.chip_sw_all_escalation_resets.1497987127 Jun 04 03:48:43 PM PDT 24 Jun 04 03:57:46 PM PDT 24 6097357650 ps
T22 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1463329992 Jun 04 03:29:58 PM PDT 24 Jun 04 03:34:29 PM PDT 24 3088824376 ps
T265 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2275393491 Jun 04 03:32:51 PM PDT 24 Jun 04 03:43:29 PM PDT 24 5962523862 ps
T606 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3940830858 Jun 04 03:20:38 PM PDT 24 Jun 04 04:18:54 PM PDT 24 15013144856 ps
T607 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3455364871 Jun 04 03:42:38 PM PDT 24 Jun 04 05:02:50 PM PDT 24 22826092760 ps
T356 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.1850383495 Jun 04 03:28:24 PM PDT 24 Jun 04 03:56:48 PM PDT 24 7576569960 ps
T27 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3746691561 Jun 04 03:31:42 PM PDT 24 Jun 04 03:38:50 PM PDT 24 4219110977 ps
T608 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3987384093 Jun 04 03:38:01 PM PDT 24 Jun 04 03:44:47 PM PDT 24 4709775940 ps
T609 /workspace/coverage/default/0.chip_sw_aes_enc.2100969350 Jun 04 03:16:38 PM PDT 24 Jun 04 03:22:11 PM PDT 24 3222081480 ps
T198 /workspace/coverage/default/2.chip_sw_edn_boot_mode.1575845010 Jun 04 03:36:33 PM PDT 24 Jun 04 03:48:45 PM PDT 24 3210290930 ps
T610 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3879093520 Jun 04 03:13:29 PM PDT 24 Jun 04 03:28:10 PM PDT 24 8318024352 ps
T611 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2894571993 Jun 04 03:34:07 PM PDT 24 Jun 04 03:41:14 PM PDT 24 6484788020 ps
T612 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.799224155 Jun 04 03:28:50 PM PDT 24 Jun 04 03:38:59 PM PDT 24 6375125640 ps
T613 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.232200624 Jun 04 03:18:03 PM PDT 24 Jun 04 03:26:44 PM PDT 24 5845777012 ps
T614 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2382519059 Jun 04 03:15:26 PM PDT 24 Jun 04 03:34:22 PM PDT 24 7379084702 ps
T615 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2259965206 Jun 04 03:20:53 PM PDT 24 Jun 04 03:25:23 PM PDT 24 3581564536 ps
T616 /workspace/coverage/default/1.rom_e2e_asm_init_dev.1870601263 Jun 04 03:35:06 PM PDT 24 Jun 04 04:29:13 PM PDT 24 14215474762 ps
T113 /workspace/coverage/default/2.chip_tap_straps_prod.709697478 Jun 04 03:37:10 PM PDT 24 Jun 04 03:56:00 PM PDT 24 10061585072 ps
T442 /workspace/coverage/default/63.chip_sw_all_escalation_resets.3863383307 Jun 04 03:48:46 PM PDT 24 Jun 04 03:56:52 PM PDT 24 4102648040 ps
T617 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1794612182 Jun 04 03:42:18 PM PDT 24 Jun 04 03:57:01 PM PDT 24 8861554449 ps
T313 /workspace/coverage/default/1.chip_sw_pattgen_ios.1379945807 Jun 04 03:17:34 PM PDT 24 Jun 04 03:21:44 PM PDT 24 3181707386 ps
T171 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.510634074 Jun 04 03:37:40 PM PDT 24 Jun 04 03:48:56 PM PDT 24 8638100405 ps
T482 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.223379440 Jun 04 03:50:36 PM PDT 24 Jun 04 03:57:16 PM PDT 24 3523215336 ps
T618 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1830807546 Jun 04 03:39:52 PM PDT 24 Jun 04 03:49:28 PM PDT 24 6850895137 ps
T619 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1424816765 Jun 04 03:14:34 PM PDT 24 Jun 04 03:48:25 PM PDT 24 9201870640 ps
T176 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2406103724 Jun 04 03:47:25 PM PDT 24 Jun 04 03:52:48 PM PDT 24 4247632724 ps
T620 /workspace/coverage/default/1.chip_sw_aes_idle.3383420127 Jun 04 03:23:41 PM PDT 24 Jun 04 03:29:06 PM PDT 24 2900311950 ps
T473 /workspace/coverage/default/14.chip_sw_all_escalation_resets.1502192359 Jun 04 03:44:15 PM PDT 24 Jun 04 03:55:58 PM PDT 24 4486333088 ps
T146 /workspace/coverage/default/1.chip_sw_flash_init.873608442 Jun 04 03:20:58 PM PDT 24 Jun 04 03:55:21 PM PDT 24 16801411445 ps
T621 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.208567656 Jun 04 03:14:10 PM PDT 24 Jun 04 03:34:15 PM PDT 24 17584768078 ps
T175 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1050526581 Jun 04 03:50:19 PM PDT 24 Jun 04 03:55:59 PM PDT 24 3340083418 ps
T513 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1578568295 Jun 04 03:51:08 PM PDT 24 Jun 04 03:58:04 PM PDT 24 3264765000 ps
T622 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3641108066 Jun 04 03:13:20 PM PDT 24 Jun 04 03:37:00 PM PDT 24 8239928248 ps
T366 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.651360655 Jun 04 03:28:55 PM PDT 24 Jun 04 03:34:24 PM PDT 24 2847714146 ps
T623 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1115497824 Jun 04 03:14:13 PM PDT 24 Jun 04 03:50:21 PM PDT 24 22280005390 ps
T624 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2050984194 Jun 04 03:14:37 PM PDT 24 Jun 04 03:24:16 PM PDT 24 3739131376 ps
T465 /workspace/coverage/default/40.chip_sw_all_escalation_resets.4142697900 Jun 04 03:47:30 PM PDT 24 Jun 04 03:55:44 PM PDT 24 5126996760 ps
T474 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1353366160 Jun 04 03:51:29 PM PDT 24 Jun 04 03:58:42 PM PDT 24 4175401432 ps
T625 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2619671193 Jun 04 03:31:02 PM PDT 24 Jun 04 04:02:06 PM PDT 24 8449832070 ps
T200 /workspace/coverage/default/1.chip_plic_all_irqs_0.1839995870 Jun 04 03:27:11 PM PDT 24 Jun 04 03:46:16 PM PDT 24 6023283032 ps
T133 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3153356585 Jun 04 03:17:47 PM PDT 24 Jun 04 03:27:51 PM PDT 24 4503269398 ps
T493 /workspace/coverage/default/15.chip_sw_all_escalation_resets.2186810348 Jun 04 03:45:43 PM PDT 24 Jun 04 03:54:30 PM PDT 24 6169296372 ps
T364 /workspace/coverage/default/0.chip_sival_flash_info_access.3551359685 Jun 04 03:16:57 PM PDT 24 Jun 04 03:23:18 PM PDT 24 3403808392 ps
T438 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1196654895 Jun 04 03:46:54 PM PDT 24 Jun 04 03:52:57 PM PDT 24 4121705438 ps
T626 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3750584856 Jun 04 03:16:38 PM PDT 24 Jun 04 03:24:27 PM PDT 24 4820767328 ps
T627 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2908341149 Jun 04 03:20:16 PM PDT 24 Jun 04 04:26:49 PM PDT 24 14228329100 ps
T382 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.736553634 Jun 04 03:38:35 PM PDT 24 Jun 04 03:49:09 PM PDT 24 6116042374 ps
T101 /workspace/coverage/default/2.chip_tap_straps_rma.2007856897 Jun 04 03:36:57 PM PDT 24 Jun 04 03:40:26 PM PDT 24 3431631038 ps
T628 /workspace/coverage/default/0.rom_e2e_smoke.1217203405 Jun 04 03:19:18 PM PDT 24 Jun 04 04:15:00 PM PDT 24 13688745240 ps
T629 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1901353303 Jun 04 03:44:26 PM PDT 24 Jun 04 04:39:45 PM PDT 24 18321557272 ps
T630 /workspace/coverage/default/0.rom_e2e_asm_init_rma.562253751 Jun 04 03:20:08 PM PDT 24 Jun 04 04:33:39 PM PDT 24 14017409224 ps
T318 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.4069455569 Jun 04 03:30:08 PM PDT 24 Jun 04 03:33:28 PM PDT 24 2717221412 ps
T349 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3613507565 Jun 04 03:14:04 PM PDT 24 Jun 04 03:32:51 PM PDT 24 8277987240 ps
T449 /workspace/coverage/default/52.chip_sw_all_escalation_resets.1468987379 Jun 04 03:48:34 PM PDT 24 Jun 04 04:00:47 PM PDT 24 5429117028 ps
T325 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1802313135 Jun 04 03:14:52 PM PDT 24 Jun 04 04:04:24 PM PDT 24 20893304872 ps
T631 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1712143354 Jun 04 03:45:03 PM PDT 24 Jun 04 04:58:48 PM PDT 24 22154463332 ps
T340 /workspace/coverage/default/82.chip_sw_all_escalation_resets.3196907455 Jun 04 03:53:30 PM PDT 24 Jun 04 04:01:15 PM PDT 24 4410672698 ps
T452 /workspace/coverage/default/21.chip_sw_all_escalation_resets.2174916313 Jun 04 03:45:04 PM PDT 24 Jun 04 03:52:54 PM PDT 24 5005807638 ps
T215 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1375608459 Jun 04 03:14:59 PM PDT 24 Jun 04 03:31:16 PM PDT 24 5108567002 ps
T632 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2113197695 Jun 04 03:42:25 PM PDT 24 Jun 04 03:52:55 PM PDT 24 7935409928 ps
T633 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.206466382 Jun 04 03:18:22 PM PDT 24 Jun 04 06:24:37 PM PDT 24 66215983696 ps
T634 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3184915673 Jun 04 03:26:40 PM PDT 24 Jun 04 03:40:21 PM PDT 24 8443489416 ps
T425 /workspace/coverage/default/2.rom_volatile_raw_unlock.1385472269 Jun 04 03:39:52 PM PDT 24 Jun 04 03:41:51 PM PDT 24 2455097641 ps
T182 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.416787678 Jun 04 03:16:34 PM PDT 24 Jun 04 03:27:33 PM PDT 24 5584129500 ps
T635 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1501684358 Jun 04 03:45:35 PM PDT 24 Jun 04 03:55:56 PM PDT 24 4138921192 ps
T226 /workspace/coverage/default/0.chip_sw_usbdev_vbus.79459946 Jun 04 03:16:21 PM PDT 24 Jun 04 03:19:47 PM PDT 24 3342260608 ps
T636 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3581569334 Jun 04 03:36:55 PM PDT 24 Jun 04 04:05:55 PM PDT 24 9279288240 ps
T189 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.4218295871 Jun 04 03:26:27 PM PDT 24 Jun 04 03:35:16 PM PDT 24 4618027880 ps
T637 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3683503917 Jun 04 03:37:36 PM PDT 24 Jun 04 03:40:49 PM PDT 24 2405511080 ps
T638 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2635639246 Jun 04 03:21:04 PM PDT 24 Jun 04 03:28:52 PM PDT 24 5013090059 ps
T639 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.364791504 Jun 04 03:44:00 PM PDT 24 Jun 04 04:42:48 PM PDT 24 15379914728 ps
T476 /workspace/coverage/default/53.chip_sw_all_escalation_resets.436909523 Jun 04 03:48:50 PM PDT 24 Jun 04 03:57:43 PM PDT 24 4726075932 ps
T136 /workspace/coverage/default/0.chip_plic_all_irqs_10.779563734 Jun 04 03:13:41 PM PDT 24 Jun 04 03:22:16 PM PDT 24 4053327400 ps
T640 /workspace/coverage/default/1.chip_sw_aes_masking_off.3573352139 Jun 04 03:24:55 PM PDT 24 Jun 04 03:29:32 PM PDT 24 3383709312 ps
T102 /workspace/coverage/default/3.chip_tap_straps_rma.882644035 Jun 04 03:42:51 PM PDT 24 Jun 04 03:50:37 PM PDT 24 5593821008 ps
T641 /workspace/coverage/default/2.chip_sival_flash_info_access.3742153090 Jun 04 03:31:38 PM PDT 24 Jun 04 03:36:35 PM PDT 24 3135335264 ps
T93 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.824427102 Jun 04 03:15:08 PM PDT 24 Jun 04 03:21:27 PM PDT 24 5662298028 ps
T379 /workspace/coverage/default/20.chip_sw_all_escalation_resets.1187150538 Jun 04 03:44:57 PM PDT 24 Jun 04 03:54:52 PM PDT 24 4933507976 ps
T355 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1862650529 Jun 04 03:22:30 PM PDT 24 Jun 04 03:32:06 PM PDT 24 3922325136 ps
T642 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.4210344886 Jun 04 03:13:19 PM PDT 24 Jun 04 03:22:30 PM PDT 24 7561656200 ps
T496 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.4234692563 Jun 04 03:50:25 PM PDT 24 Jun 04 03:56:58 PM PDT 24 3685021326 ps
T643 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1313766288 Jun 04 03:31:12 PM PDT 24 Jun 04 03:37:20 PM PDT 24 3485242096 ps
T644 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3430058514 Jun 04 03:14:15 PM PDT 24 Jun 04 03:25:07 PM PDT 24 5292487736 ps
T645 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1646900861 Jun 04 03:27:48 PM PDT 24 Jun 04 03:50:55 PM PDT 24 7360116387 ps
T646 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3781102242 Jun 04 03:14:07 PM PDT 24 Jun 04 03:20:53 PM PDT 24 5351768950 ps
T470 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2855591546 Jun 04 03:48:24 PM PDT 24 Jun 04 03:54:20 PM PDT 24 3297832930 ps
T195 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1052170458 Jun 04 03:25:35 PM PDT 24 Jun 04 03:34:32 PM PDT 24 4991683612 ps
T647 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2333255191 Jun 04 03:16:12 PM PDT 24 Jun 04 03:20:30 PM PDT 24 3053624720 ps
T142 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3911684541 Jun 04 03:13:11 PM PDT 24 Jun 04 03:20:41 PM PDT 24 4088097792 ps
T368 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.774022264 Jun 04 03:23:27 PM PDT 24 Jun 04 03:39:52 PM PDT 24 5310021968 ps
T466 /workspace/coverage/default/11.chip_sw_all_escalation_resets.130413034 Jun 04 03:44:08 PM PDT 24 Jun 04 03:52:37 PM PDT 24 5321916172 ps
T64 /workspace/coverage/default/2.chip_jtag_csr_rw.2211413051 Jun 04 03:30:12 PM PDT 24 Jun 04 03:56:18 PM PDT 24 12763210244 ps
T648 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1093612125 Jun 04 03:20:44 PM PDT 24 Jun 04 03:27:13 PM PDT 24 3757181624 ps
T649 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.256991668 Jun 04 03:44:00 PM PDT 24 Jun 04 04:27:46 PM PDT 24 11179457120 ps
T650 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3479123888 Jun 04 03:18:03 PM PDT 24 Jun 04 03:24:03 PM PDT 24 6407277382 ps
T352 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.798307271 Jun 04 03:31:40 PM PDT 24 Jun 04 03:43:25 PM PDT 24 3717288952 ps
T651 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2502469917 Jun 04 03:45:22 PM PDT 24 Jun 04 04:06:15 PM PDT 24 8407924080 ps
T652 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2895453855 Jun 04 03:20:19 PM PDT 24 Jun 04 04:05:32 PM PDT 24 11684349304 ps
T479 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3971227425 Jun 04 03:38:40 PM PDT 24 Jun 04 03:46:51 PM PDT 24 3980583800 ps
T653 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2072465969 Jun 04 03:27:38 PM PDT 24 Jun 04 03:39:03 PM PDT 24 3548784776 ps
T201 /workspace/coverage/default/0.chip_plic_all_irqs_0.356543877 Jun 04 03:14:04 PM PDT 24 Jun 04 03:32:24 PM PDT 24 5647250044 ps
T65 /workspace/coverage/default/2.chip_jtag_mem_access.4116645826 Jun 04 03:30:15 PM PDT 24 Jun 04 03:55:14 PM PDT 24 13494554016 ps
T491 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.4198990822 Jun 04 03:51:32 PM PDT 24 Jun 04 03:55:54 PM PDT 24 3478180560 ps
T116 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3886802724 Jun 04 03:23:46 PM PDT 24 Jun 04 03:43:17 PM PDT 24 12036787646 ps
T483 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1392623219 Jun 04 03:50:10 PM PDT 24 Jun 04 03:57:12 PM PDT 24 3851077776 ps
T654 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2826533177 Jun 04 03:21:36 PM PDT 24 Jun 04 03:29:51 PM PDT 24 5149490718 ps
T524 /workspace/coverage/default/24.chip_sw_all_escalation_resets.949721458 Jun 04 03:45:56 PM PDT 24 Jun 04 03:54:36 PM PDT 24 6007297024 ps
T655 /workspace/coverage/default/1.chip_tap_straps_rma.2627370977 Jun 04 03:27:34 PM PDT 24 Jun 04 03:41:10 PM PDT 24 8858387240 ps
T656 /workspace/coverage/default/4.chip_tap_straps_rma.1719421367 Jun 04 03:41:24 PM PDT 24 Jun 04 03:49:30 PM PDT 24 5789773478 ps
T657 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.4281475394 Jun 04 03:14:43 PM PDT 24 Jun 04 03:17:51 PM PDT 24 2990961658 ps
T658 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.68224806 Jun 04 03:22:28 PM PDT 24 Jun 04 03:33:09 PM PDT 24 7767682764 ps
T288 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3398219101 Jun 04 03:26:08 PM PDT 24 Jun 04 03:35:30 PM PDT 24 3398470159 ps
T659 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.171522447 Jun 04 03:28:45 PM PDT 24 Jun 04 03:38:40 PM PDT 24 5951937096 ps
T660 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.4282464863 Jun 04 03:37:36 PM PDT 24 Jun 04 03:41:14 PM PDT 24 2994468182 ps
T353 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2589499432 Jun 04 03:31:09 PM PDT 24 Jun 04 03:45:15 PM PDT 24 4428816431 ps
T661 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3793718365 Jun 04 03:43:14 PM PDT 24 Jun 04 04:07:33 PM PDT 24 7639239630 ps
T662 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2996112272 Jun 04 03:19:41 PM PDT 24 Jun 04 03:29:27 PM PDT 24 3770337310 ps
T178 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1658141375 Jun 04 03:20:27 PM PDT 24 Jun 04 03:22:16 PM PDT 24 2087036624 ps
T663 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3274759658 Jun 04 03:37:27 PM PDT 24 Jun 04 03:44:12 PM PDT 24 2786423672 ps
T664 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3768901823 Jun 04 03:43:18 PM PDT 24 Jun 04 04:38:37 PM PDT 24 14211834835 ps
T665 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1479429259 Jun 04 03:22:40 PM PDT 24 Jun 04 04:17:37 PM PDT 24 13404654563 ps
T10 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3042562591 Jun 04 03:16:00 PM PDT 24 Jun 04 03:19:38 PM PDT 24 3805184112 ps
T410 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3045857425 Jun 04 03:15:16 PM PDT 24 Jun 04 03:47:08 PM PDT 24 10331698338 ps
T187 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.4009087098 Jun 04 03:16:38 PM PDT 24 Jun 04 03:19:07 PM PDT 24 3612112099 ps
T411 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1641497124 Jun 04 03:14:46 PM PDT 24 Jun 04 03:35:41 PM PDT 24 6188555528 ps
T412 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2666085138 Jun 04 03:20:38 PM PDT 24 Jun 04 04:15:45 PM PDT 24 13774020025 ps
T291 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2100141135 Jun 04 03:43:27 PM PDT 24 Jun 04 03:49:43 PM PDT 24 4127224314 ps
T236 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1416697406 Jun 04 03:20:44 PM PDT 24 Jun 04 05:05:16 PM PDT 24 50720714696 ps
T413 /workspace/coverage/default/0.chip_sw_rv_timer_irq.1411883646 Jun 04 03:12:49 PM PDT 24 Jun 04 03:16:36 PM PDT 24 3036614308 ps
T371 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.46826432 Jun 04 03:22:00 PM PDT 24 Jun 04 03:51:58 PM PDT 24 11361610671 ps
T332 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2942818967 Jun 04 03:36:46 PM PDT 24 Jun 04 04:14:26 PM PDT 24 13035494316 ps
T666 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3624506228 Jun 04 03:32:52 PM PDT 24 Jun 04 03:37:17 PM PDT 24 2822353808 ps
T667 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.339989027 Jun 04 03:28:20 PM PDT 24 Jun 04 03:36:57 PM PDT 24 4757466208 ps
T289 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4256082918 Jun 04 03:41:41 PM PDT 24 Jun 04 03:50:51 PM PDT 24 5570146807 ps
T668 /workspace/coverage/default/0.chip_sw_edn_sw_mode.3170244358 Jun 04 03:13:37 PM PDT 24 Jun 04 03:55:41 PM PDT 24 9266085568 ps
T669 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3305850642 Jun 04 03:27:29 PM PDT 24 Jun 04 03:37:41 PM PDT 24 4366163000 ps
T670 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3699136850 Jun 04 03:15:24 PM PDT 24 Jun 04 03:19:08 PM PDT 24 2571072906 ps
T671 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1022167029 Jun 04 03:44:20 PM PDT 24 Jun 04 04:06:27 PM PDT 24 8752451872 ps
T672 /workspace/coverage/default/0.chip_sw_otbn_smoketest.50585389 Jun 04 03:18:04 PM PDT 24 Jun 04 03:35:14 PM PDT 24 5278178192 ps
T532 /workspace/coverage/default/35.chip_sw_all_escalation_resets.2602390963 Jun 04 03:47:37 PM PDT 24 Jun 04 03:59:56 PM PDT 24 5265889332 ps
T673 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1151830421 Jun 04 03:31:27 PM PDT 24 Jun 04 03:41:51 PM PDT 24 4047792211 ps
T433 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4071773135 Jun 04 03:53:15 PM PDT 24 Jun 04 03:59:50 PM PDT 24 3760501490 ps
T674 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.670770356 Jun 04 03:17:41 PM PDT 24 Jun 04 03:26:40 PM PDT 24 5389352448 ps
T385 /workspace/coverage/default/33.chip_sw_all_escalation_resets.9108780 Jun 04 03:50:50 PM PDT 24 Jun 04 04:02:28 PM PDT 24 5697386478 ps
T232 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2614206450 Jun 04 03:32:56 PM PDT 24 Jun 04 03:38:16 PM PDT 24 2641449620 ps
T391 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2769683169 Jun 04 03:14:43 PM PDT 24 Jun 04 03:17:28 PM PDT 24 2364210202 ps
T675 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1363253818 Jun 04 03:23:01 PM PDT 24 Jun 04 03:41:12 PM PDT 24 5611736152 ps
T676 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.334474549 Jun 04 03:33:33 PM PDT 24 Jun 04 03:41:44 PM PDT 24 5840779882 ps
T453 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3304558506 Jun 04 03:47:26 PM PDT 24 Jun 04 03:53:33 PM PDT 24 3659888466 ps
T194 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.177057966 Jun 04 03:11:46 PM PDT 24 Jun 04 04:46:37 PM PDT 24 42730106194 ps
T677 /workspace/coverage/default/0.chip_sw_uart_smoketest.1744994553 Jun 04 03:23:45 PM PDT 24 Jun 04 03:28:12 PM PDT 24 2991514672 ps
T213 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.886616793 Jun 04 03:18:24 PM PDT 24 Jun 04 03:27:50 PM PDT 24 4560961304 ps
T372 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1198299645 Jun 04 03:14:49 PM PDT 24 Jun 04 03:41:56 PM PDT 24 12954322634 ps
T678 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1644781816 Jun 04 03:35:44 PM PDT 24 Jun 04 04:15:43 PM PDT 24 12472273733 ps
T679 /workspace/coverage/default/1.chip_sw_edn_auto_mode.2166039955 Jun 04 03:24:17 PM PDT 24 Jun 04 04:04:06 PM PDT 24 8325785646 ps
T680 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3620374538 Jun 04 03:13:30 PM PDT 24 Jun 04 03:18:39 PM PDT 24 3171139468 ps
T681 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.612294874 Jun 04 03:19:43 PM PDT 24 Jun 04 03:39:12 PM PDT 24 4845783170 ps
T165 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.968803369 Jun 04 03:25:15 PM PDT 24 Jun 04 03:36:07 PM PDT 24 7199180892 ps
T23 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3345271933 Jun 04 03:19:11 PM PDT 24 Jun 04 03:24:21 PM PDT 24 2947022249 ps
T238 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.105101182 Jun 04 03:37:56 PM PDT 24 Jun 04 04:12:34 PM PDT 24 22864961216 ps
T682 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.286760313 Jun 04 03:26:27 PM PDT 24 Jun 04 04:33:46 PM PDT 24 19232543991 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%