Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.12 90.71 80.62 90.04 92.03 96.47 84.87


Total test records in report: 988
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T683 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2510286461 Jun 04 03:27:53 PM PDT 24 Jun 04 03:46:18 PM PDT 24 8275091704 ps
T358 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2254511709 Jun 04 03:20:08 PM PDT 24 Jun 04 03:31:28 PM PDT 24 3667571000 ps
T684 /workspace/coverage/default/2.chip_sw_hmac_smoketest.4224482868 Jun 04 03:39:48 PM PDT 24 Jun 04 03:45:19 PM PDT 24 3533508600 ps
T514 /workspace/coverage/default/66.chip_sw_all_escalation_resets.1294209421 Jun 04 03:50:40 PM PDT 24 Jun 04 03:58:16 PM PDT 24 5284982192 ps
T685 /workspace/coverage/default/4.chip_tap_straps_prod.1297760482 Jun 04 03:42:27 PM PDT 24 Jun 04 03:44:51 PM PDT 24 2434231295 ps
T686 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1308833190 Jun 04 03:13:51 PM PDT 24 Jun 04 06:54:45 PM PDT 24 78175994176 ps
T687 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2674190794 Jun 04 03:42:49 PM PDT 24 Jun 04 03:51:05 PM PDT 24 4499933428 ps
T688 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.797204992 Jun 04 03:34:55 PM PDT 24 Jun 04 03:41:19 PM PDT 24 3650641962 ps
T689 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2803057606 Jun 04 03:35:33 PM PDT 24 Jun 04 04:28:44 PM PDT 24 11210781865 ps
T690 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.316617582 Jun 04 03:41:46 PM PDT 24 Jun 04 04:53:07 PM PDT 24 20696790956 ps
T71 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2953658129 Jun 04 03:15:43 PM PDT 24 Jun 04 03:19:33 PM PDT 24 2193256995 ps
T255 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3304430752 Jun 04 03:19:35 PM PDT 24 Jun 04 04:55:35 PM PDT 24 22799990806 ps
T354 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2718092871 Jun 04 03:18:04 PM PDT 24 Jun 04 03:28:31 PM PDT 24 4039601724 ps
T51 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3296078045 Jun 04 03:22:40 PM PDT 24 Jun 04 03:29:33 PM PDT 24 5557663784 ps
T691 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.403830413 Jun 04 03:26:04 PM PDT 24 Jun 04 03:30:51 PM PDT 24 3429386448 ps
T692 /workspace/coverage/default/2.chip_sw_example_concurrency.4108497853 Jun 04 03:33:16 PM PDT 24 Jun 04 03:38:37 PM PDT 24 3304265816 ps
T693 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.986855843 Jun 04 03:37:09 PM PDT 24 Jun 04 04:34:34 PM PDT 24 15252268444 ps
T362 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3869133701 Jun 04 03:15:13 PM PDT 24 Jun 04 03:27:26 PM PDT 24 19115515868 ps
T694 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2981268049 Jun 04 03:30:45 PM PDT 24 Jun 04 03:34:08 PM PDT 24 2912764560 ps
T695 /workspace/coverage/default/0.chip_sw_kmac_idle.2962564715 Jun 04 03:13:04 PM PDT 24 Jun 04 03:17:33 PM PDT 24 3059269324 ps
T696 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1697645094 Jun 04 03:37:37 PM PDT 24 Jun 04 03:59:11 PM PDT 24 6553994216 ps
T697 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3254639373 Jun 04 03:40:31 PM PDT 24 Jun 04 03:49:03 PM PDT 24 6673988200 ps
T698 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3560098991 Jun 04 03:29:39 PM PDT 24 Jun 04 03:39:39 PM PDT 24 4058841814 ps
T699 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3117532011 Jun 04 03:42:50 PM PDT 24 Jun 04 03:51:00 PM PDT 24 4039551496 ps
T700 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2744168367 Jun 04 03:23:52 PM PDT 24 Jun 04 04:08:23 PM PDT 24 13868314465 ps
T701 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.584135829 Jun 04 03:16:23 PM PDT 24 Jun 04 03:26:01 PM PDT 24 4571544360 ps
T217 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.4137061350 Jun 04 03:19:48 PM PDT 24 Jun 04 03:33:57 PM PDT 24 5330963756 ps
T66 /workspace/coverage/default/0.chip_jtag_mem_access.1992016811 Jun 04 03:06:00 PM PDT 24 Jun 04 03:33:37 PM PDT 24 13906863724 ps
T702 /workspace/coverage/default/0.chip_sw_edn_auto_mode.1410513281 Jun 04 03:13:19 PM PDT 24 Jun 04 03:24:55 PM PDT 24 3534831640 ps
T703 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1524226971 Jun 04 03:37:47 PM PDT 24 Jun 04 03:46:16 PM PDT 24 4490604226 ps
T704 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3504980409 Jun 04 03:14:08 PM PDT 24 Jun 04 03:23:43 PM PDT 24 6321066034 ps
T443 /workspace/coverage/default/25.chip_sw_all_escalation_resets.1095379878 Jun 04 03:48:27 PM PDT 24 Jun 04 04:00:46 PM PDT 24 6171460560 ps
T705 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3536214385 Jun 04 03:37:05 PM PDT 24 Jun 04 03:57:09 PM PDT 24 6974447372 ps
T266 /workspace/coverage/default/10.chip_sw_all_escalation_resets.2776577397 Jun 04 03:43:52 PM PDT 24 Jun 04 03:54:31 PM PDT 24 5949416800 ps
T706 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3915994024 Jun 04 03:32:36 PM PDT 24 Jun 04 03:47:34 PM PDT 24 5564008550 ps
T707 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.276717609 Jun 04 03:15:38 PM PDT 24 Jun 04 03:29:30 PM PDT 24 7168352684 ps
T708 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2686211474 Jun 04 03:30:36 PM PDT 24 Jun 04 03:55:49 PM PDT 24 8509589702 ps
T709 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.41107567 Jun 04 03:21:15 PM PDT 24 Jun 04 04:18:17 PM PDT 24 13128209508 ps
T710 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3214457973 Jun 04 03:23:53 PM PDT 24 Jun 04 04:11:05 PM PDT 24 15326715140 ps
T398 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1796067102 Jun 04 03:38:22 PM PDT 24 Jun 04 04:38:35 PM PDT 24 25494240756 ps
T509 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2469130878 Jun 04 03:51:00 PM PDT 24 Jun 04 03:57:43 PM PDT 24 3471874164 ps
T711 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.142167254 Jun 04 03:18:48 PM PDT 24 Jun 04 03:24:56 PM PDT 24 2894547920 ps
T114 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3404839326 Jun 04 03:13:47 PM PDT 24 Jun 04 03:22:21 PM PDT 24 3596285800 ps
T712 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.165782875 Jun 04 03:36:36 PM PDT 24 Jun 04 03:57:55 PM PDT 24 13956624227 ps
T713 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1322015069 Jun 04 03:15:37 PM PDT 24 Jun 04 03:21:19 PM PDT 24 2460948740 ps
T714 /workspace/coverage/default/2.chip_sw_example_flash.512125909 Jun 04 03:30:16 PM PDT 24 Jun 04 03:33:21 PM PDT 24 3075354132 ps
T715 /workspace/coverage/default/0.chip_sw_hmac_smoketest.2404878629 Jun 04 03:18:15 PM PDT 24 Jun 04 03:23:02 PM PDT 24 3060797464 ps
T527 /workspace/coverage/default/51.chip_sw_all_escalation_resets.1621284193 Jun 04 03:47:48 PM PDT 24 Jun 04 03:57:09 PM PDT 24 5917224280 ps
T426 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3579386177 Jun 04 03:21:11 PM PDT 24 Jun 04 03:22:59 PM PDT 24 2158617095 ps
T716 /workspace/coverage/default/0.chip_sw_example_flash.2491813718 Jun 04 03:13:29 PM PDT 24 Jun 04 03:17:10 PM PDT 24 2216565500 ps
T53 /workspace/coverage/default/1.chip_sw_spi_device_tpm.3802657839 Jun 04 03:20:23 PM PDT 24 Jun 04 03:25:08 PM PDT 24 3242790458 ps
T717 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2853183079 Jun 04 03:14:34 PM PDT 24 Jun 04 03:20:09 PM PDT 24 3108453702 ps
T134 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1139509675 Jun 04 03:19:16 PM PDT 24 Jun 04 03:27:05 PM PDT 24 4339740669 ps
T718 /workspace/coverage/default/2.chip_sw_example_manufacturer.4264787714 Jun 04 03:31:22 PM PDT 24 Jun 04 03:36:04 PM PDT 24 2793778740 ps
T719 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.553183674 Jun 04 03:38:41 PM PDT 24 Jun 04 03:44:21 PM PDT 24 3110057658 ps
T720 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.298454894 Jun 04 03:16:18 PM PDT 24 Jun 04 03:20:32 PM PDT 24 3201715760 ps
T439 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3012573060 Jun 04 03:46:49 PM PDT 24 Jun 04 03:53:30 PM PDT 24 3830976090 ps
T427 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.587702648 Jun 04 03:12:51 PM PDT 24 Jun 04 03:14:38 PM PDT 24 3024346032 ps
T179 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3527271419 Jun 04 03:32:06 PM PDT 24 Jun 04 03:36:07 PM PDT 24 2710966149 ps
T454 /workspace/coverage/default/90.chip_sw_all_escalation_resets.3197860686 Jun 04 03:52:27 PM PDT 24 Jun 04 03:59:10 PM PDT 24 4805822008 ps
T721 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1645713285 Jun 04 03:36:23 PM PDT 24 Jun 04 03:40:36 PM PDT 24 2636180696 ps
T722 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.4197763582 Jun 04 03:32:03 PM PDT 24 Jun 04 03:53:53 PM PDT 24 11491575668 ps
T46 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3160728694 Jun 04 03:33:06 PM PDT 24 Jun 04 03:36:51 PM PDT 24 2769584250 ps
T519 /workspace/coverage/default/57.chip_sw_all_escalation_resets.2919623292 Jun 04 03:51:04 PM PDT 24 Jun 04 03:58:09 PM PDT 24 4470719336 ps
T239 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.791498777 Jun 04 03:15:22 PM PDT 24 Jun 04 04:47:14 PM PDT 24 46196958724 ps
T723 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3721101518 Jun 04 03:43:45 PM PDT 24 Jun 04 03:51:01 PM PDT 24 3955668698 ps
T227 /workspace/coverage/default/0.chip_sw_usbdev_stream.3445776802 Jun 04 03:14:37 PM PDT 24 Jun 04 04:37:30 PM PDT 24 18492334988 ps
T724 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2661688835 Jun 04 03:17:45 PM PDT 24 Jun 04 04:07:19 PM PDT 24 11035557734 ps
T725 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3090837297 Jun 04 03:22:31 PM PDT 24 Jun 04 04:15:03 PM PDT 24 20623902590 ps
T726 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3112983548 Jun 04 03:28:57 PM PDT 24 Jun 04 03:33:50 PM PDT 24 3513825084 ps
T521 /workspace/coverage/default/74.chip_sw_all_escalation_resets.3784019708 Jun 04 03:51:11 PM PDT 24 Jun 04 04:02:05 PM PDT 24 5037963864 ps
T218 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2276441073 Jun 04 03:32:14 PM PDT 24 Jun 04 03:45:00 PM PDT 24 4835725316 ps
T727 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.910856664 Jun 04 03:17:32 PM PDT 24 Jun 04 03:20:28 PM PDT 24 2471927528 ps
T728 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3591876995 Jun 04 03:40:36 PM PDT 24 Jun 04 03:50:43 PM PDT 24 4351114904 ps
T729 /workspace/coverage/default/0.chip_sw_power_idle_load.1099000631 Jun 04 03:14:42 PM PDT 24 Jun 04 03:23:59 PM PDT 24 4192409764 ps
T730 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1020942865 Jun 04 03:37:31 PM PDT 24 Jun 04 03:46:47 PM PDT 24 5030903472 ps
T731 /workspace/coverage/default/1.chip_sw_example_manufacturer.3440231082 Jun 04 03:18:17 PM PDT 24 Jun 04 03:21:57 PM PDT 24 2970885440 ps
T732 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.394296966 Jun 04 03:21:52 PM PDT 24 Jun 04 04:45:48 PM PDT 24 22122577004 ps
T534 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1596783917 Jun 04 03:47:18 PM PDT 24 Jun 04 03:52:48 PM PDT 24 3565917112 ps
T9 /workspace/coverage/default/1.chip_jtag_csr_rw.938795062 Jun 04 03:20:34 PM PDT 24 Jun 04 04:03:05 PM PDT 24 23017144183 ps
T290 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2325886017 Jun 04 03:41:38 PM PDT 24 Jun 04 03:52:03 PM PDT 24 5709881660 ps
T405 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1044194827 Jun 04 03:12:13 PM PDT 24 Jun 04 03:18:55 PM PDT 24 3518824776 ps
T406 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.18200919 Jun 04 03:33:59 PM PDT 24 Jun 04 04:14:10 PM PDT 24 30632585963 ps
T300 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2657111921 Jun 04 03:28:55 PM PDT 24 Jun 04 03:33:50 PM PDT 24 3207588387 ps
T407 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3094854161 Jun 04 03:26:04 PM PDT 24 Jun 04 04:06:07 PM PDT 24 13396286520 ps
T408 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2167022547 Jun 04 03:15:29 PM PDT 24 Jun 04 03:26:09 PM PDT 24 6728300108 ps
T150 /workspace/coverage/default/73.chip_sw_all_escalation_resets.3724305558 Jun 04 03:51:33 PM PDT 24 Jun 04 04:01:15 PM PDT 24 5225808112 ps
T409 /workspace/coverage/default/1.rom_e2e_smoke.3661982219 Jun 04 03:34:27 PM PDT 24 Jun 04 04:28:03 PM PDT 24 13839509960 ps
T97 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.217763107 Jun 04 03:36:20 PM PDT 24 Jun 04 03:46:25 PM PDT 24 3694700648 ps
T733 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.421414200 Jun 04 03:31:27 PM PDT 24 Jun 04 03:38:45 PM PDT 24 3607236719 ps
T167 /workspace/coverage/default/1.chip_jtag_mem_access.4143422913 Jun 04 03:20:28 PM PDT 24 Jun 04 03:47:21 PM PDT 24 13179549472 ps
T734 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2299210322 Jun 04 03:30:53 PM PDT 24 Jun 04 03:41:07 PM PDT 24 3888071240 ps
T526 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3507464590 Jun 04 03:51:29 PM PDT 24 Jun 04 03:56:58 PM PDT 24 4131795120 ps
T735 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3084773059 Jun 04 03:45:15 PM PDT 24 Jun 04 03:54:18 PM PDT 24 4297996360 ps
T736 /workspace/coverage/default/1.chip_sw_csrng_kat_test.2990484257 Jun 04 03:24:45 PM PDT 24 Jun 04 03:30:45 PM PDT 24 3287655316 ps
T737 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.1490930890 Jun 04 03:37:45 PM PDT 24 Jun 04 03:56:40 PM PDT 24 7383396658 ps
T738 /workspace/coverage/default/4.chip_sw_uart_tx_rx.1083371502 Jun 04 03:41:59 PM PDT 24 Jun 04 03:53:54 PM PDT 24 3665960148 ps
T494 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.758048897 Jun 04 03:51:02 PM PDT 24 Jun 04 03:57:27 PM PDT 24 4144487976 ps
T475 /workspace/coverage/default/79.chip_sw_all_escalation_resets.4111961822 Jun 04 03:50:49 PM PDT 24 Jun 04 04:00:38 PM PDT 24 4901406268 ps
T739 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1030760180 Jun 04 03:22:02 PM PDT 24 Jun 04 03:40:14 PM PDT 24 7246055328 ps
T740 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.765721216 Jun 04 03:16:49 PM PDT 24 Jun 04 03:24:21 PM PDT 24 4173053224 ps
T741 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2599216952 Jun 04 03:20:55 PM PDT 24 Jun 04 03:41:50 PM PDT 24 10050600290 ps
T742 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.832787051 Jun 04 03:13:35 PM PDT 24 Jun 04 03:21:49 PM PDT 24 4748669030 ps
T522 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.643062655 Jun 04 03:45:24 PM PDT 24 Jun 04 03:53:53 PM PDT 24 4162026390 ps
T743 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1541698281 Jun 04 03:44:43 PM PDT 24 Jun 04 03:53:25 PM PDT 24 5208398620 ps
T744 /workspace/coverage/default/2.chip_sw_hmac_multistream.3821804868 Jun 04 03:35:38 PM PDT 24 Jun 04 03:56:59 PM PDT 24 7027048456 ps
T745 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.277214324 Jun 04 03:49:32 PM PDT 24 Jun 04 03:58:14 PM PDT 24 3905629670 ps
T746 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.751976566 Jun 04 03:38:54 PM PDT 24 Jun 04 03:58:45 PM PDT 24 9496016006 ps
T747 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.943065632 Jun 04 03:34:27 PM PDT 24 Jun 04 04:37:44 PM PDT 24 14278992176 ps
T748 /workspace/coverage/default/1.chip_sw_example_rom.3453402937 Jun 04 03:16:50 PM PDT 24 Jun 04 03:19:02 PM PDT 24 2493808588 ps
T267 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2213395537 Jun 04 03:14:10 PM PDT 24 Jun 04 03:22:30 PM PDT 24 4940317670 ps
T535 /workspace/coverage/default/8.chip_sw_all_escalation_resets.1800839617 Jun 04 03:43:27 PM PDT 24 Jun 04 03:55:17 PM PDT 24 5226191164 ps
T749 /workspace/coverage/default/0.chip_sw_edn_kat.220754029 Jun 04 03:14:18 PM PDT 24 Jun 04 03:26:14 PM PDT 24 3265261670 ps
T481 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.899176566 Jun 04 03:52:42 PM PDT 24 Jun 04 03:59:05 PM PDT 24 4013998234 ps
T429 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2269849891 Jun 04 03:48:57 PM PDT 24 Jun 04 03:54:46 PM PDT 24 3611091574 ps
T750 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.4141111822 Jun 04 03:24:49 PM PDT 24 Jun 04 03:28:02 PM PDT 24 3294350751 ps
T434 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.4245295478 Jun 04 03:55:09 PM PDT 24 Jun 04 04:00:55 PM PDT 24 2842787220 ps
T751 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.809880180 Jun 04 03:45:13 PM PDT 24 Jun 04 04:36:04 PM PDT 24 12639934120 ps
T752 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1251821901 Jun 04 03:22:39 PM PDT 24 Jun 04 03:32:02 PM PDT 24 8314314320 ps
T753 /workspace/coverage/default/2.rom_keymgr_functest.1633794561 Jun 04 03:46:13 PM PDT 24 Jun 04 03:56:06 PM PDT 24 4650298040 ps
T149 /workspace/coverage/default/0.chip_sw_kmac_app_rom.2397793035 Jun 04 03:12:50 PM PDT 24 Jun 04 03:15:59 PM PDT 24 2432056522 ps
T754 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2550087208 Jun 04 03:44:56 PM PDT 24 Jun 04 04:32:21 PM PDT 24 14063907760 ps
T533 /workspace/coverage/default/95.chip_sw_all_escalation_resets.2620158440 Jun 04 03:53:08 PM PDT 24 Jun 04 04:04:54 PM PDT 24 5988589946 ps
T755 /workspace/coverage/default/1.chip_sw_hmac_multistream.2162020392 Jun 04 03:25:44 PM PDT 24 Jun 04 03:50:48 PM PDT 24 6556025674 ps
T756 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3791219646 Jun 04 03:42:21 PM PDT 24 Jun 04 03:55:36 PM PDT 24 4420805864 ps
T367 /workspace/coverage/default/2.chip_sw_hmac_enc.2598037008 Jun 04 03:35:22 PM PDT 24 Jun 04 03:39:10 PM PDT 24 2241332210 ps
T444 /workspace/coverage/default/83.chip_sw_all_escalation_resets.3000115602 Jun 04 03:52:02 PM PDT 24 Jun 04 04:01:37 PM PDT 24 5155468024 ps
T757 /workspace/coverage/default/1.chip_sw_aes_smoketest.3576099292 Jun 04 03:30:40 PM PDT 24 Jun 04 03:34:30 PM PDT 24 2855755110 ps
T495 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1785911166 Jun 04 03:47:30 PM PDT 24 Jun 04 03:53:05 PM PDT 24 3382179088 ps
T758 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2139215093 Jun 04 03:12:57 PM PDT 24 Jun 04 03:21:28 PM PDT 24 4604405192 ps
T759 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1700446228 Jun 04 03:15:28 PM PDT 24 Jun 04 06:38:28 PM PDT 24 255751734904 ps
T301 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.273194259 Jun 04 03:41:12 PM PDT 24 Jun 04 03:46:28 PM PDT 24 2604236694 ps
T151 /workspace/coverage/default/76.chip_sw_all_escalation_resets.4153320284 Jun 04 03:50:42 PM PDT 24 Jun 04 04:00:50 PM PDT 24 5411662620 ps
T760 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.743689108 Jun 04 03:17:45 PM PDT 24 Jun 04 04:06:53 PM PDT 24 13302415840 ps
T761 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.275121462 Jun 04 03:14:25 PM PDT 24 Jun 04 03:25:31 PM PDT 24 8776794216 ps
T762 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3568754932 Jun 04 03:31:24 PM PDT 24 Jun 04 03:34:41 PM PDT 24 2756764528 ps
T763 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2538156855 Jun 04 03:18:50 PM PDT 24 Jun 04 03:22:26 PM PDT 24 2419784060 ps
T764 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3203072779 Jun 04 03:45:45 PM PDT 24 Jun 04 03:50:10 PM PDT 24 2963833618 ps
T765 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2669854450 Jun 04 03:21:52 PM PDT 24 Jun 04 03:38:26 PM PDT 24 7508275048 ps
T208 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1931554819 Jun 04 03:33:05 PM PDT 24 Jun 04 03:36:42 PM PDT 24 2987009432 ps
T766 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1520292556 Jun 04 03:40:41 PM PDT 24 Jun 04 03:50:21 PM PDT 24 4322346410 ps
T767 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1795465384 Jun 04 03:34:43 PM PDT 24 Jun 04 03:39:54 PM PDT 24 3156998640 ps
T768 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.4192468066 Jun 04 03:41:10 PM PDT 24 Jun 04 03:52:49 PM PDT 24 4171006913 ps
T422 /workspace/coverage/default/3.chip_tap_straps_dev.1926043884 Jun 04 03:42:59 PM PDT 24 Jun 04 03:55:08 PM PDT 24 9013563867 ps
T769 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3468184603 Jun 04 03:15:17 PM PDT 24 Jun 04 03:19:02 PM PDT 24 2686533944 ps
T770 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2321029123 Jun 04 03:16:19 PM PDT 24 Jun 04 03:25:32 PM PDT 24 6005611400 ps
T322 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3819860273 Jun 04 03:37:40 PM PDT 24 Jun 04 03:44:47 PM PDT 24 4647461800 ps
T771 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1485595377 Jun 04 03:25:13 PM PDT 24 Jun 04 03:29:11 PM PDT 24 3059166166 ps
T772 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.654426193 Jun 04 03:15:14 PM PDT 24 Jun 04 03:39:56 PM PDT 24 8600945045 ps
T477 /workspace/coverage/default/4.chip_sw_all_escalation_resets.3569639542 Jun 04 03:43:20 PM PDT 24 Jun 04 03:52:15 PM PDT 24 5182842144 ps
T119 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2905590040 Jun 04 03:51:20 PM PDT 24 Jun 04 03:58:08 PM PDT 24 4224691114 ps
T137 /workspace/coverage/default/2.chip_plic_all_irqs_10.1364608292 Jun 04 03:36:20 PM PDT 24 Jun 04 03:44:58 PM PDT 24 3630959868 ps
T773 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3696112147 Jun 04 03:46:54 PM PDT 24 Jun 04 03:55:08 PM PDT 24 3162608680 ps
T216 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1296770479 Jun 04 03:18:57 PM PDT 24 Jun 04 03:35:53 PM PDT 24 5785736472 ps
T464 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.961573249 Jun 04 03:52:11 PM PDT 24 Jun 04 03:59:09 PM PDT 24 3821834902 ps
T457 /workspace/coverage/default/31.chip_sw_all_escalation_resets.1463355162 Jun 04 03:50:01 PM PDT 24 Jun 04 04:00:04 PM PDT 24 5357200974 ps
T774 /workspace/coverage/default/1.chip_tap_straps_testunlock0.1325917458 Jun 04 03:27:55 PM PDT 24 Jun 04 03:36:37 PM PDT 24 5757027489 ps
T775 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.485964781 Jun 04 03:41:37 PM PDT 24 Jun 04 04:04:33 PM PDT 24 8441182672 ps
T143 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3067842853 Jun 04 03:37:51 PM PDT 24 Jun 04 03:47:21 PM PDT 24 4585632336 ps
T776 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.3103951694 Jun 04 03:38:18 PM PDT 24 Jun 04 03:44:11 PM PDT 24 3370258354 ps
T777 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3047120147 Jun 04 03:16:30 PM PDT 24 Jun 04 03:22:59 PM PDT 24 6076657382 ps
T778 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1229652779 Jun 04 03:21:35 PM PDT 24 Jun 04 03:31:02 PM PDT 24 4326044186 ps
T503 /workspace/coverage/default/96.chip_sw_all_escalation_resets.1432134075 Jun 04 03:53:03 PM PDT 24 Jun 04 04:02:44 PM PDT 24 5556528872 ps
T506 /workspace/coverage/default/75.chip_sw_all_escalation_resets.1628961474 Jun 04 03:52:54 PM PDT 24 Jun 04 04:01:12 PM PDT 24 5588103048 ps
T779 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1858627364 Jun 04 03:39:36 PM PDT 24 Jun 04 03:50:18 PM PDT 24 5369409944 ps
T780 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.388971054 Jun 04 03:26:47 PM PDT 24 Jun 04 03:34:11 PM PDT 24 3350097832 ps
T781 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3175181785 Jun 04 03:24:28 PM PDT 24 Jun 04 03:31:28 PM PDT 24 3196055780 ps
T334 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1273838870 Jun 04 03:14:20 PM PDT 24 Jun 04 04:28:59 PM PDT 24 16764246066 ps
T430 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3425724203 Jun 04 03:47:39 PM PDT 24 Jun 04 03:52:55 PM PDT 24 3349818728 ps
T782 /workspace/coverage/default/0.chip_sw_aes_masking_off.2597127055 Jun 04 03:13:43 PM PDT 24 Jun 04 03:19:31 PM PDT 24 2834037557 ps
T214 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3921974723 Jun 04 03:13:26 PM PDT 24 Jun 04 03:28:00 PM PDT 24 4821677906 ps
T783 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.783784294 Jun 04 03:25:50 PM PDT 24 Jun 04 04:03:57 PM PDT 24 10526695414 ps
T501 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2138886881 Jun 04 03:52:27 PM PDT 24 Jun 04 03:59:01 PM PDT 24 4121732206 ps
T507 /workspace/coverage/default/65.chip_sw_all_escalation_resets.729150982 Jun 04 03:49:41 PM PDT 24 Jun 04 03:59:22 PM PDT 24 5353294366 ps
T784 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2319956211 Jun 04 03:22:08 PM PDT 24 Jun 04 03:38:35 PM PDT 24 6475647144 ps
T492 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2613230064 Jun 04 03:48:21 PM PDT 24 Jun 04 03:53:37 PM PDT 24 2937762182 ps
T785 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.732126370 Jun 04 03:37:15 PM PDT 24 Jun 04 03:48:59 PM PDT 24 4998737276 ps
T258 /workspace/coverage/default/0.chip_sw_plic_sw_irq.4032518667 Jun 04 03:14:56 PM PDT 24 Jun 04 03:20:28 PM PDT 24 3071974362 ps
T786 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3766282360 Jun 04 03:37:47 PM PDT 24 Jun 04 03:41:24 PM PDT 24 2477730200 ps
T499 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.778809414 Jun 04 03:46:01 PM PDT 24 Jun 04 03:53:44 PM PDT 24 3900989820 ps
T183 /workspace/coverage/default/87.chip_sw_all_escalation_resets.2710231517 Jun 04 03:51:18 PM PDT 24 Jun 04 03:59:17 PM PDT 24 5757561184 ps
T357 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.3386472782 Jun 04 03:35:32 PM PDT 24 Jun 04 03:56:40 PM PDT 24 5997738094 ps
T787 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.194676048 Jun 04 03:18:39 PM PDT 24 Jun 04 03:22:45 PM PDT 24 3516894750 ps
T788 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1061698231 Jun 04 03:34:01 PM PDT 24 Jun 04 06:55:09 PM PDT 24 254849507632 ps
T789 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1413397932 Jun 04 03:23:16 PM PDT 24 Jun 04 03:29:03 PM PDT 24 6353487824 ps
T512 /workspace/coverage/default/0.chip_sw_all_escalation_resets.1823430136 Jun 04 03:16:52 PM PDT 24 Jun 04 03:27:14 PM PDT 24 5017683314 ps
T790 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1228105654 Jun 04 03:43:45 PM PDT 24 Jun 04 03:51:40 PM PDT 24 6994757514 ps
T791 /workspace/coverage/default/2.rom_e2e_asm_init_prod.2535969314 Jun 04 03:45:18 PM PDT 24 Jun 04 04:47:59 PM PDT 24 13833652921 ps
T490 /workspace/coverage/default/92.chip_sw_all_escalation_resets.482701614 Jun 04 03:52:44 PM PDT 24 Jun 04 04:02:09 PM PDT 24 5452798216 ps
T471 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2882885723 Jun 04 03:46:58 PM PDT 24 Jun 04 03:54:41 PM PDT 24 3569080298 ps
T792 /workspace/coverage/default/4.chip_tap_straps_dev.110029252 Jun 04 03:41:20 PM PDT 24 Jun 04 03:51:51 PM PDT 24 6916292888 ps
T193 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.4226719592 Jun 04 03:18:26 PM PDT 24 Jun 04 04:40:09 PM PDT 24 43376363214 ps
T126 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3154654567 Jun 04 03:28:10 PM PDT 24 Jun 04 03:58:50 PM PDT 24 21759432004 ps
T500 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1897766424 Jun 04 03:44:45 PM PDT 24 Jun 04 03:49:53 PM PDT 24 3313436550 ps
T793 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.1977484284 Jun 04 03:27:09 PM PDT 24 Jun 04 03:30:49 PM PDT 24 2694089011 ps
T502 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1929178171 Jun 04 03:52:21 PM PDT 24 Jun 04 03:58:28 PM PDT 24 3722897674 ps
T794 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2064291165 Jun 04 03:23:25 PM PDT 24 Jun 04 04:15:10 PM PDT 24 14401690200 ps
T795 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.280272511 Jun 04 03:35:38 PM PDT 24 Jun 04 03:44:41 PM PDT 24 8359207237 ps
T196 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.959456232 Jun 04 03:40:41 PM PDT 24 Jun 04 03:47:09 PM PDT 24 4231225484 ps
T516 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3450703989 Jun 04 03:49:36 PM PDT 24 Jun 04 03:58:22 PM PDT 24 3281588028 ps
T796 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3655022731 Jun 04 03:15:01 PM PDT 24 Jun 04 03:56:05 PM PDT 24 22506011239 ps
T797 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1201057620 Jun 04 03:25:49 PM PDT 24 Jun 04 03:40:32 PM PDT 24 6107628236 ps
T798 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3965864127 Jun 04 03:39:01 PM PDT 24 Jun 04 03:59:11 PM PDT 24 5343489896 ps
T799 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3085545630 Jun 04 03:29:10 PM PDT 24 Jun 04 03:33:03 PM PDT 24 2416835586 ps
T120 /workspace/coverage/default/67.chip_sw_all_escalation_resets.3526101095 Jun 04 03:50:16 PM PDT 24 Jun 04 03:59:24 PM PDT 24 4477103320 ps
T800 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3171623175 Jun 04 03:22:26 PM PDT 24 Jun 04 03:35:25 PM PDT 24 8323299465 ps
T233 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4084464724 Jun 04 03:21:44 PM PDT 24 Jun 04 03:48:13 PM PDT 24 24545010726 ps
T801 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3322359146 Jun 04 03:26:11 PM PDT 24 Jun 04 03:36:15 PM PDT 24 9626235688 ps
T127 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3641895973 Jun 04 03:38:21 PM PDT 24 Jun 04 04:04:21 PM PDT 24 25113185996 ps
T530 /workspace/coverage/default/28.chip_sw_all_escalation_resets.4214213690 Jun 04 03:45:49 PM PDT 24 Jun 04 03:56:51 PM PDT 24 6758166132 ps
T259 /workspace/coverage/default/2.chip_sw_plic_sw_irq.1769796272 Jun 04 03:36:23 PM PDT 24 Jun 04 03:40:14 PM PDT 24 3230925928 ps
T234 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2825669355 Jun 04 03:22:26 PM PDT 24 Jun 04 03:27:32 PM PDT 24 3121716294 ps
T802 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1374459160 Jun 04 03:45:17 PM PDT 24 Jun 04 04:33:40 PM PDT 24 11442701856 ps
T803 /workspace/coverage/default/1.chip_sw_hmac_enc.2386687083 Jun 04 03:25:55 PM PDT 24 Jun 04 03:30:48 PM PDT 24 2982038920 ps
T804 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1135801207 Jun 04 03:25:33 PM PDT 24 Jun 04 03:59:44 PM PDT 24 10289757995 ps
T805 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2312871460 Jun 04 03:36:55 PM PDT 24 Jun 04 03:49:34 PM PDT 24 4548997560 ps
T806 /workspace/coverage/default/2.chip_sw_otbn_smoketest.2269980574 Jun 04 03:46:26 PM PDT 24 Jun 04 04:01:52 PM PDT 24 5691451512 ps
T807 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1227220500 Jun 04 03:44:43 PM PDT 24 Jun 04 04:22:32 PM PDT 24 12748389304 ps
T808 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2006384287 Jun 04 03:36:00 PM PDT 24 Jun 04 03:47:42 PM PDT 24 7368639892 ps
T809 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2847240948 Jun 04 03:35:43 PM PDT 24 Jun 04 04:05:25 PM PDT 24 9196920480 ps
T515 /workspace/coverage/default/17.chip_sw_all_escalation_resets.1109865474 Jun 04 03:47:41 PM PDT 24 Jun 04 03:59:05 PM PDT 24 4687579030 ps
T810 /workspace/coverage/default/1.rom_keymgr_functest.1224172645 Jun 04 03:30:16 PM PDT 24 Jun 04 03:39:13 PM PDT 24 4451599010 ps
T423 /workspace/coverage/default/0.chip_tap_straps_dev.3751906528 Jun 04 03:15:13 PM PDT 24 Jun 04 03:34:46 PM PDT 24 10238645884 ps
T47 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3869245039 Jun 04 03:18:43 PM PDT 24 Jun 04 03:23:21 PM PDT 24 2884421170 ps
T811 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.594626061 Jun 04 03:15:39 PM PDT 24 Jun 04 04:14:32 PM PDT 24 18094145890 ps
T812 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2724302604 Jun 04 03:20:25 PM PDT 24 Jun 04 03:43:13 PM PDT 24 6029148827 ps
T813 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.1123221030 Jun 04 03:30:43 PM PDT 24 Jun 04 03:34:53 PM PDT 24 2707053278 ps
T814 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3806779673 Jun 04 03:17:59 PM PDT 24 Jun 04 03:28:12 PM PDT 24 3292206582 ps
T815 /workspace/coverage/default/2.chip_sw_gpio_smoketest.300412819 Jun 04 03:40:18 PM PDT 24 Jun 04 03:44:20 PM PDT 24 3107346720 ps
T816 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3599957860 Jun 04 03:35:21 PM PDT 24 Jun 04 03:47:37 PM PDT 24 19133247732 ps
T16 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2778662691 Jun 04 03:28:20 PM PDT 24 Jun 04 03:55:46 PM PDT 24 24682217934 ps
T24 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2901968434 Jun 04 03:13:30 PM PDT 24 Jun 04 03:17:57 PM PDT 24 2552494384 ps
T817 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2203524297 Jun 04 03:36:30 PM PDT 24 Jun 04 03:50:54 PM PDT 24 7836995944 ps
T205 /workspace/coverage/default/2.chip_plic_all_irqs_20.3913940712 Jun 04 03:36:44 PM PDT 24 Jun 04 03:50:37 PM PDT 24 4802921580 ps
T818 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.824584697 Jun 04 03:41:23 PM PDT 24 Jun 04 03:48:15 PM PDT 24 3608638640 ps
T819 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.4129755429 Jun 04 03:14:16 PM PDT 24 Jun 04 03:19:41 PM PDT 24 3463357830 ps
T820 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.504123207 Jun 04 03:42:46 PM PDT 24 Jun 04 03:50:13 PM PDT 24 4146679968 ps
T821 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2484578721 Jun 04 03:14:43 PM PDT 24 Jun 04 03:21:10 PM PDT 24 3379548194 ps
T822 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.615342040 Jun 04 03:44:36 PM PDT 24 Jun 04 03:58:37 PM PDT 24 12830204026 ps
T823 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.444483618 Jun 04 03:31:39 PM PDT 24 Jun 04 03:37:14 PM PDT 24 3002327640 ps
T824 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.776511826 Jun 04 03:14:32 PM PDT 24 Jun 04 03:22:18 PM PDT 24 4067365280 ps
T825 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2687634336 Jun 04 03:22:52 PM PDT 24 Jun 04 03:34:49 PM PDT 24 5219415992 ps
T154 /workspace/coverage/default/0.chip_jtag_csr_rw.3954766890 Jun 04 03:06:00 PM PDT 24 Jun 04 03:10:52 PM PDT 24 4179320498 ps
T826 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.899138095 Jun 04 03:13:47 PM PDT 24 Jun 04 03:18:26 PM PDT 24 3292432713 ps
T827 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3416897826 Jun 04 03:19:39 PM PDT 24 Jun 04 03:42:54 PM PDT 24 7590278860 ps
T828 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1004563247 Jun 04 03:20:26 PM PDT 24 Jun 04 03:25:47 PM PDT 24 2947722920 ps
T829 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1651894094 Jun 04 03:14:15 PM PDT 24 Jun 04 03:24:23 PM PDT 24 4310128120 ps
T830 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1728002568 Jun 04 03:20:51 PM PDT 24 Jun 04 03:23:21 PM PDT 24 3532611736 ps
T831 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.331080444 Jun 04 03:36:31 PM PDT 24 Jun 04 04:07:43 PM PDT 24 27952004233 ps
T832 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.1433500299 Jun 04 03:33:51 PM PDT 24 Jun 04 03:47:06 PM PDT 24 6158167664 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%