Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3449836	1			T73	103		T74	1478		T75	203
values[2]	714798	1			T73	41		T74	419		T75	47
values[3]	102886	1			T73	1		T74	151		T75	1
values[4]	54590	1			T74	5		T128	340		T536	14
values[5]	36608	1			T128	172		T536	14		T537	87
values[6]	27384	1			T128	120		T536	14		T537	28
values[7]	21965	1			T128	78		T536	14		T537	24
values[8]	18598	1			T128	33		T536	14		T537	26
values[9]	16743	1			T128	36		T536	14		T537	21
values[10]	15094	1			T128	31		T536	14		T537	15
values[11]	13665	1			T128	15		T536	14		T537	14
values[12]	12837	1			T128	16		T536	14		T537	17
values[13]	12533	1			T128	15		T536	14		T537	21
values[14]	11831	1			T128	4		T536	14		T537	24
values[15]	11486	1			T128	10		T536	14		T537	34
values[16]	11082	1			T128	10		T536	14		T537	30
values[17]	10663	1			T128	4		T536	14		T537	26
values[18]	10173	1			T128	4		T536	14		T537	12
values[19]	9912	1			T128	2		T536	14		T537	12
values[20]	9877	1			T128	2		T536	14		T537	15
values[21]	9286	1			T128	3		T536	14		T537	23
values[22]	8924	1			T128	2		T536	15		T537	20
values[23]	8548	1			T128	3		T536	14		T537	16
values[24]	8632	1			T128	3		T536	14		T537	16
values[25]	8301	1			T128	5		T536	14		T537	29
values[26]	8017	1			T128	2		T536	14		T537	18
values[27]	7574	1			T128	2		T536	14		T537	15
values[28]	7115	1			T128	2		T536	14		T537	10
values[29]	6622	1			T128	3		T536	14		T537	9
values[30]	6168	1			T128	3		T536	14		T537	7
values[31]	5939	1			T128	3		T536	15		T537	10
values[32]	5605	1			T128	2		T536	14		T537	6
values[33]	5089	1			T128	2		T536	15		T537	6
values[34]	4710	1			T128	3		T536	14		T537	11
values[35]	4362	1			T128	2		T536	15		T537	15
values[36]	4270	1			T128	3		T536	14		T537	15
values[37]	3966	1			T128	3		T536	14		T537	6
values[38]	3683	1			T128	4		T536	14		T537	8
values[39]	3632	1			T128	4		T536	14		T537	4
values[40]	3469	1			T128	4		T536	14		T537	3
values[41]	3435	1			T128	2		T536	14		T537	7
values[42]	3408	1			T128	2		T536	14		T537	3
values[43]	3293	1			T128	3		T536	15		T537	7
values[44]	3096	1			T128	5		T536	14		T537	5
values[45]	3090	1			T128	2		T536	15		T537	10
values[46]	2970	1			T128	2		T536	14		T537	13
values[47]	2906	1			T128	2		T536	14		T537	7
values[48]	2864	1			T128	4		T536	15		T537	7
values[49]	2811	1			T128	3		T536	14		T537	12
values[50]	2846	1			T128	6		T536	15		T537	8
values[51]	2806	1			T128	8		T536	14		T537	10
values[52]	2737	1			T128	4		T536	15		T537	4
values[53]	2636	1			T128	5		T536	14		T537	8
values[54]	2698	1			T128	4		T536	14		T537	13
values[55]	2576	1			T128	5		T536	14		T537	20
values[56]	2539	1			T128	3		T536	14		T537	10
values[57]	2412	1			T128	5		T536	14		T537	9
values[58]	2469	1			T128	5		T536	14		T537	14
values[59]	2477	1			T128	4		T536	14		T537	6
values[60]	2439	1			T128	3		T536	15		T537	6
values[61]	2752	1			T128	4		T536	14		T537	4
values[62]	4321	1			T128	8		T536	14		T537	5
values[63]	17822	1			T128	61		T536	169		T537	20
values[64]	229132	1			T128	258		T536	2398		T537	111

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4496392	1			T73	156		T74	1595		T75	271
values[2]	761848	1			T73	40		T74	459		T75	61
values[3]	72728	1			T73	3		T74	134		T75	2
values[4]	14101	1			T74	46		T128	43		T536	42
values[5]	5417	1			T74	15		T128	10		T536	8
values[6]	3209	1			T74	3		T128	3		T536	1
values[7]	2443	1			T128	1		T537	8		T541	2
values[8]	2031	1			T128	3		T537	6		T541	2
values[9]	1809	1			T128	1		T537	11		T541	1
values[10]	1519	1			T128	2		T537	12		T541	1
values[11]	1425	1			T128	1		T537	19		T541	1
values[12]	1299	1			T128	4		T537	10		T541	1
values[13]	1199	1			T128	8		T537	6		T541	1
values[14]	1116	1			T128	4		T537	8		T541	1
values[15]	1011	1			T128	1		T537	3		T541	1
values[16]	932	1			T128	2		T537	6		T541	1
values[17]	909	1			T128	1		T537	10		T541	1
values[18]	875	1			T128	6		T537	12		T541	1
values[19]	805	1			T128	4		T537	13		T541	1
values[20]	840	1			T128	1		T537	5		T541	1
values[21]	788	1			T128	3		T537	11		T541	1
values[22]	762	1			T128	1		T537	7		T541	1
values[23]	708	1			T128	1		T537	6		T541	1
values[24]	675	1			T128	1		T537	9		T541	1
values[25]	738	1			T128	1		T537	7		T541	1
values[26]	701	1			T128	4		T537	10		T541	1
values[27]	711	1			T128	1		T537	12		T541	1
values[28]	736	1			T128	2		T537	4		T541	1
values[29]	650	1			T128	3		T537	8		T541	1
values[30]	588	1			T128	1		T537	4		T541	1
values[31]	591	1			T128	3		T537	2		T541	1
values[32]	584	1			T128	2		T537	1		T541	1
values[33]	590	1			T128	1		T537	1		T541	1
values[34]	511	1			T128	4		T537	1		T541	1
values[35]	456	1			T128	1		T537	2		T541	1
values[36]	505	1			T128	1		T537	1		T541	1
values[37]	505	1			T128	7		T537	3		T541	1
values[38]	490	1			T128	5		T537	8		T541	1
values[39]	488	1			T128	5		T537	10		T541	1
values[40]	465	1			T128	4		T537	3		T541	1
values[41]	433	1			T128	3		T537	1		T541	1
values[42]	428	1			T128	1		T537	2		T541	1
values[43]	455	1			T128	2		T537	1		T541	1
values[44]	421	1			T128	2		T537	1		T541	1
values[45]	372	1			T128	2		T541	1		T640	1
values[46]	380	1			T128	1		T541	1		T640	1
values[47]	383	1			T128	1		T541	1		T640	1
values[48]	419	1			T128	2		T541	1		T640	1
values[49]	420	1			T128	3		T541	1		T640	2
values[50]	413	1			T128	3		T541	1		T640	4
values[51]	410	1			T128	3		T541	1		T640	2
values[52]	398	1			T128	5		T541	1		T640	7
values[53]	351	1			T128	1		T541	1		T640	2
values[54]	348	1			T128	1		T541	1		T640	3
values[55]	339	1			T128	6		T541	1		T640	3
values[56]	382	1			T128	12		T541	1		T640	1
values[57]	353	1			T128	15		T541	1		T640	5
values[58]	344	1			T128	18		T541	1		T640	1
values[59]	329	1			T128	4		T541	1		T640	2
values[60]	343	1			T128	5		T541	1		T640	3
values[61]	368	1			T128	2		T541	1		T640	1
values[62]	599	1			T541	1		T640	1		T750	2
values[63]	2767	1			T541	1		T640	3		T750	5
values[64]	22194	1			T541	180		T640	7		T750	155

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	528884	1			T73	1		T74	15		T75	3
values[2]	2487003	1			T73	34		T74	495		T75	113
values[3]	1083260	1			T73	133		T74	1454		T75	224
values[4]	142303	1			T73	4		T74	304		T75	9
values[5]	71771	1			T74	7		T128	557		T536	14
values[6]	47133	1			T128	374		T536	14		T537	268
values[7]	34641	1			T128	232		T536	14		T537	196
values[8]	27179	1			T128	200		T536	14		T537	78
values[9]	22973	1			T128	155		T536	14		T537	44
values[10]	20310	1			T128	126		T536	14		T537	28
values[11]	18191	1			T128	118		T536	14		T537	12
values[12]	16413	1			T128	97		T536	14		T537	10
values[13]	15574	1			T128	120		T536	14		T537	8
values[14]	14525	1			T128	113		T536	14		T537	7
values[15]	13984	1			T128	105		T536	14		T537	6
values[16]	13332	1			T128	76		T536	14		T537	15
values[17]	12842	1			T128	63		T536	14		T537	21
values[18]	12006	1			T128	62		T536	14		T537	12
values[19]	11635	1			T128	22		T536	14		T537	23
values[20]	11186	1			T128	38		T536	14		T537	24
values[21]	10428	1			T128	24		T536	14		T537	22
values[22]	10129	1			T128	23		T536	14		T537	27
values[23]	10044	1			T128	24		T536	14		T537	21
values[24]	9686	1			T128	14		T536	15		T537	8
values[25]	9032	1			T128	19		T536	14		T537	10
values[26]	8644	1			T128	15		T536	14		T537	7
values[27]	8112	1			T128	14		T536	14		T537	10
values[28]	7870	1			T128	10		T536	14		T537	25
values[29]	7441	1			T128	16		T536	15		T537	10
values[30]	6965	1			T128	14		T536	14		T537	6
values[31]	6615	1			T128	14		T536	14		T537	9
values[32]	6003	1			T128	13		T536	14		T537	7
values[33]	5661	1			T128	12		T536	14		T537	12
values[34]	5229	1			T128	12		T536	14		T537	7
values[35]	4931	1			T128	13		T536	14		T537	11
values[36]	4548	1			T128	10		T536	15		T537	10
values[37]	4293	1			T128	10		T536	16		T537	8
values[38]	4127	1			T128	11		T536	14		T537	16
values[39]	3968	1			T128	13		T536	14		T537	25
values[40]	3780	1			T128	11		T536	14		T537	15
values[41]	3797	1			T128	15		T536	14		T537	10
values[42]	3690	1			T128	11		T536	14		T537	6
values[43]	3478	1			T128	7		T536	14		T537	9
values[44]	3416	1			T128	12		T536	14		T537	4
values[45]	3477	1			T128	18		T536	14		T537	2
values[46]	3320	1			T128	15		T536	14		T537	3
values[47]	3257	1			T128	9		T536	14		T537	3
values[48]	3150	1			T128	20		T536	14		T537	2
values[49]	3070	1			T128	22		T536	14		T537	1
values[50]	3077	1			T128	12		T536	14		T537	2
values[51]	3112	1			T128	7		T536	14		T537	5
values[52]	3129	1			T128	6		T536	14		T537	8
values[53]	3037	1			T128	10		T536	14		T537	3
values[54]	2957	1			T128	16		T536	14		T537	1
values[55]	2896	1			T128	17		T536	14		T537	2
values[56]	2908	1			T128	35		T536	15		T537	2
values[57]	2795	1			T128	19		T536	14		T537	2
values[58]	2753	1			T128	13		T536	14		T537	7
values[59]	2725	1			T128	11		T536	14		T537	11
values[60]	2690	1			T128	14		T536	14		T537	5
values[61]	2863	1			T128	9		T536	14		T537	1
values[62]	4014	1			T128	12		T536	14		T537	6
values[63]	18283	1			T128	42		T536	279		T537	4
values[64]	218118	1			T128	126		T536	2451		T537	6