Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2525294	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

34471480

1

T4

121849

T5

78504

T6

6235

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	25473734	1			T4	107450		T5	67452		T6	1148
values[0x0]	9604914	1			T4	14399		T5	11052		T6	5087
values[0x1]	1918126	1			T4	8		T5	2		T6	71

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	701574	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36295200

1

T4

121857

T5

78506

T6

6306

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17249705	1			T4	60929		T5	39253		T6	3153
valid_sources[0x01]	17248712	1			T4	60928		T5	39253		T6	3153
valid_sources[0x02]	39419	1			T550	5		T150	354		T151	157
valid_sources[0x03]	40284	1			T550	41		T150	393		T151	178
valid_sources[0x04]	40739	1			T149	1		T550	4		T150	385
valid_sources[0x05]	40341	1			T76	1		T550	13		T150	424
valid_sources[0x06]	39994	1			T550	15		T150	428		T151	179
valid_sources[0x07]	40788	1			T76	2		T149	1		T550	1
valid_sources[0x08]	40781	1			T550	61		T150	395		T151	155
valid_sources[0x09]	40980	1			T68	1		T76	1		T550	473
valid_sources[0x0a]	40835	1			T550	7		T150	425		T151	152
valid_sources[0x0b]	40317	1			T550	11		T150	391		T151	186
valid_sources[0x0c]	40283	1			T68	1		T550	23		T150	429
valid_sources[0x0d]	39758	1			T550	6		T150	359		T151	149
valid_sources[0x0e]	41109	1			T76	1		T550	61		T150	371
valid_sources[0x0f]	40346	1			T68	1		T550	20		T150	433
valid_sources[0x10]	41416	1			T68	3		T76	1		T550	13
valid_sources[0x11]	40596	1			T68	1		T76	1		T149	1
valid_sources[0x12]	39293	1			T68	1		T550	6		T150	407
valid_sources[0x13]	39891	1			T68	1		T149	1		T550	2
valid_sources[0x14]	39626	1			T68	1		T76	1		T550	10
valid_sources[0x15]	40374	1			T10	39		T149	2		T150	403
valid_sources[0x16]	39928	1			T68	4		T550	15		T150	339
valid_sources[0x17]	40340	1			T76	1		T550	8		T150	403
valid_sources[0x18]	39332	1			T68	1		T550	6		T150	407
valid_sources[0x19]	40590	1			T68	4		T76	1		T197	39
valid_sources[0x1a]	40046	1			T76	1		T550	5		T150	393
valid_sources[0x1b]	39031	1			T68	2		T76	2		T550	30
valid_sources[0x1c]	39762	1			T76	1		T550	35		T150	385
valid_sources[0x1d]	40873	1			T68	1		T76	1		T149	7
valid_sources[0x1e]	40063	1			T76	1		T550	18		T150	406
valid_sources[0x1f]	40507	1			T76	2		T550	15		T150	398
valid_sources[0x20]	39926	1			T76	2		T550	27		T150	315

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24661178

1

T4

107450

T5

67452

T6

1148

values[0x0]

all_enables

biggest_size

9565939

1

T4

14399

T5

11052

T6

5087

values[0x1]

all_enables

biggest_size

244363

1

T68

28

T76

17

T77

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2705316	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

428201

1

T73

20

T74

291

T75

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1060323	1			T73	44		T74	674		T75	8
values[0x0]	1012291	1			T73	60		T74	669		T75	1
values[0x1]	1060903	1			T73	41		T74	710		T75	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2095651	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1037866

1

T73

40

T74

706

T75

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48496	1			T74	32		T127	2		T128	11
valid_sources[0x01]	48320	1			T74	46		T127	1		T128	8
valid_sources[0x02]	49528	1			T74	58		T127	2		T128	9
valid_sources[0x03]	48865	1			T74	44		T75	1		T127	2
valid_sources[0x04]	48580	1			T73	6		T74	57		T127	2
valid_sources[0x05]	48872	1			T74	27		T127	1		T128	15
valid_sources[0x06]	48877	1			T74	23		T75	1		T128	8
valid_sources[0x07]	48525	1			T74	25		T75	1		T128	6
valid_sources[0x08]	49347	1			T74	16		T127	6		T128	8
valid_sources[0x09]	48325	1			T73	8		T74	36		T127	2
valid_sources[0x0a]	48276	1			T73	9		T74	17		T127	2
valid_sources[0x0b]	48588	1			T73	23		T74	30		T127	1
valid_sources[0x0c]	49484	1			T74	27		T75	1		T127	6
valid_sources[0x0d]	48840	1			T74	40		T128	11		T536	50
valid_sources[0x0e]	50341	1			T74	22		T127	3		T128	8
valid_sources[0x0f]	48772	1			T73	2		T74	23		T127	3
valid_sources[0x10]	49060	1			T74	34		T127	19		T128	7
valid_sources[0x11]	48826	1			T73	1		T74	26		T127	2
valid_sources[0x12]	48678	1			T73	2		T74	45		T127	2
valid_sources[0x13]	48340	1			T74	27		T127	4		T128	6
valid_sources[0x14]	48916	1			T73	13		T74	22		T127	3
valid_sources[0x15]	49441	1			T74	52		T127	5		T128	11
valid_sources[0x16]	48756	1			T74	31		T75	1		T127	2
valid_sources[0x17]	48562	1			T74	26		T127	3		T128	10
valid_sources[0x18]	48664	1			T74	27		T127	6		T128	8
valid_sources[0x19]	48818	1			T74	40		T127	2		T128	15
valid_sources[0x1a]	50116	1			T74	33		T75	2		T127	2
valid_sources[0x1b]	49122	1			T73	9		T74	19		T127	4
valid_sources[0x1c]	49575	1			T74	18		T127	2		T128	13
valid_sources[0x1d]	48544	1			T73	5		T74	37		T127	3
valid_sources[0x1e]	49442	1			T73	2		T74	49		T127	2
valid_sources[0x1f]	48308	1			T73	3		T74	37		T75	1
valid_sources[0x20]	48629	1			T74	31		T127	15		T128	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44861

1

T73

1

T74

28

T75

1

values[0x0]

all_enables

biggest_size

338220

1

T73

18

T74

233

T127

24

values[0x1]

all_enables

biggest_size

45120

1

T73

1

T74

30

T127

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2891954	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

470026

1

T73

19

T74

315

T75

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1150573	1			T73	63		T74	758		T75	6
values[0x0]	1060595	1			T73	52		T74	755		T75	3
values[0x1]	1150812	1			T73	84		T74	739		T75	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2219304	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1142676

1

T73

56

T74

759

T75

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51717	1			T73	2		T74	35		T127	6
valid_sources[0x01]	52340	1			T73	1		T74	40		T127	18
valid_sources[0x02]	51671	1			T73	5		T74	28		T127	14
valid_sources[0x03]	52217	1			T73	4		T74	35		T127	15
valid_sources[0x04]	52802	1			T73	3		T74	48		T127	5
valid_sources[0x05]	52065	1			T73	8		T74	41		T127	28
valid_sources[0x06]	52698	1			T73	4		T74	40		T127	8
valid_sources[0x07]	52938	1			T73	1		T74	43		T127	4
valid_sources[0x08]	53041	1			T73	1		T74	30		T127	3
valid_sources[0x09]	51275	1			T73	2		T74	26		T127	19
valid_sources[0x0a]	51833	1			T73	4		T74	28		T75	1
valid_sources[0x0b]	52287	1			T73	6		T74	29		T127	9
valid_sources[0x0c]	52918	1			T73	1		T74	42		T127	22
valid_sources[0x0d]	52351	1			T73	7		T74	24		T75	1
valid_sources[0x0e]	52503	1			T73	2		T74	35		T127	9
valid_sources[0x0f]	52635	1			T73	2		T74	33		T127	5
valid_sources[0x10]	52367	1			T73	2		T74	31		T75	1
valid_sources[0x11]	51316	1			T73	5		T74	34		T127	14
valid_sources[0x12]	53682	1			T74	33		T127	16		T128	8
valid_sources[0x13]	52110	1			T73	10		T74	41		T127	14
valid_sources[0x14]	52729	1			T73	1		T74	36		T127	3
valid_sources[0x15]	51858	1			T73	5		T74	36		T127	24
valid_sources[0x16]	53202	1			T73	1		T74	41		T75	1
valid_sources[0x17]	52522	1			T73	2		T74	36		T75	1
valid_sources[0x18]	52915	1			T73	9		T74	30		T127	7
valid_sources[0x19]	52220	1			T73	1		T74	39		T75	1
valid_sources[0x1a]	51707	1			T73	5		T74	32		T127	7
valid_sources[0x1b]	52415	1			T73	5		T74	42		T127	1
valid_sources[0x1c]	53310	1			T73	3		T74	35		T127	4
valid_sources[0x1d]	52198	1			T74	36		T127	6		T128	5
valid_sources[0x1e]	52804	1			T73	1		T74	37		T127	6
valid_sources[0x1f]	52769	1			T73	3		T74	35		T75	1
valid_sources[0x20]	52213	1			T73	3		T74	34		T127	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49172

1

T73

1

T74

33

T75

2

values[0x0]

all_enables

biggest_size

371581

1

T73

16

T74

256

T75

2

values[0x1]

all_enables

biggest_size

49273

1

T73

2

T74

26

T127

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2726283	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

430914

1

T73

22

T74

284

T75

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1067781	1			T73	61		T74	800		T75	4
values[0x0]	1020335	1			T73	63		T74	711		T75	1
values[0x1]	1069081	1			T73	48		T74	764		T75	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2111714	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1045483

1

T73

54

T74

733

T75

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48411	1			T73	2		T74	63		T128	20
valid_sources[0x01]	49084	1			T73	2		T74	38		T127	4
valid_sources[0x02]	49613	1			T73	2		T74	52		T127	2
valid_sources[0x03]	49540	1			T73	3		T74	43		T128	8
valid_sources[0x04]	48917	1			T73	3		T74	43		T128	6
valid_sources[0x05]	48429	1			T74	36		T127	9		T128	6
valid_sources[0x06]	49130	1			T73	2		T74	26		T127	1
valid_sources[0x07]	48576	1			T73	1		T74	37		T127	4
valid_sources[0x08]	48865	1			T73	4		T74	40		T127	7
valid_sources[0x09]	48327	1			T73	4		T74	17		T127	16
valid_sources[0x0a]	48744	1			T73	1		T74	34		T75	1
valid_sources[0x0b]	48906	1			T73	6		T74	50		T128	5
valid_sources[0x0c]	50324	1			T74	34		T128	10		T440	1
valid_sources[0x0d]	48558	1			T73	8		T74	81		T127	12
valid_sources[0x0e]	49849	1			T73	2		T74	39		T75	1
valid_sources[0x0f]	49025	1			T73	1		T74	43		T75	1
valid_sources[0x10]	49503	1			T73	10		T74	24		T127	8
valid_sources[0x11]	48695	1			T74	86		T75	1		T127	4
valid_sources[0x12]	50279	1			T74	35		T128	14		T440	1
valid_sources[0x13]	48192	1			T74	18		T127	12		T128	10
valid_sources[0x14]	50329	1			T73	6		T74	58		T127	1
valid_sources[0x15]	50229	1			T73	3		T74	83		T127	5
valid_sources[0x16]	48757	1			T73	4		T74	18		T127	4
valid_sources[0x17]	49130	1			T73	5		T74	22		T127	5
valid_sources[0x18]	49725	1			T73	1		T74	36		T128	11
valid_sources[0x19]	48932	1			T73	5		T74	22		T127	1
valid_sources[0x1a]	49880	1			T74	40		T128	7		T440	1
valid_sources[0x1b]	48994	1			T73	1		T74	28		T75	1
valid_sources[0x1c]	48967	1			T73	2		T74	25		T127	1
valid_sources[0x1d]	49579	1			T73	2		T74	25		T127	4
valid_sources[0x1e]	49085	1			T74	19		T127	1		T128	3
valid_sources[0x1f]	49856	1			T73	3		T74	22		T127	1
valid_sources[0x20]	48702	1			T73	1		T74	14		T127	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45385

1

T73

2

T74

32

T75

1

values[0x0]

all_enables

biggest_size

340538

1

T73

16

T74

220

T75

1

values[0x1]

all_enables

biggest_size

44991

1

T73

4

T74

32

T127

6