Module Definition
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Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.25 99.77 97.22 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_tlul_data_integ_dec 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.41 100.00 69.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_tlul_data_integ_dec 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.97 100.00 99.90 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_tlul_data_integ_dec 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.36 100.00 100.00 u_reg_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_tlul_data_integ_dec 100.00 100.00

Line Coverage for Module : tlul_cmd_intg_chk
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2211100.00
CONT_ASSIGN4400
CONT_ASSIGN4911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
44 unreachable
49 1 1


Assert Coverage for Module : tlul_cmd_intg_chk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayLoadWidthCheck 9649 9649 0 0


PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 9649 9649 0 0
T4 4 4 0 0
T5 4 4 0 0
T6 4 4 0 0
T17 4 4 0 0
T18 4 4 0 0
T44 4 4 0 0
T45 4 4 0 0
T56 4 4 0 0
T59 4 4 0 0
T82 4 4 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2211100.00
CONT_ASSIGN4400
CONT_ASSIGN4911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
44 unreachable
49 1 1


Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayLoadWidthCheck 2885 2885 0 0


PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 2885 2885 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T44 1 1 0 0
T45 1 1 0 0
T56 1 1 0 0
T59 1 1 0 0
T82 1 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2211100.00
CONT_ASSIGN4400
CONT_ASSIGN4911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
44 unreachable
49 1 1


Assert Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayLoadWidthCheck 994 994 0 0


PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 994 994 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T44 1 1 0 0
T45 1 1 0 0
T56 1 1 0 0
T59 1 1 0 0
T82 1 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2211100.00
CONT_ASSIGN4400
CONT_ASSIGN4911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
44 unreachable
49 1 1


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayLoadWidthCheck 2885 2885 0 0


PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 2885 2885 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T44 1 1 0 0
T45 1 1 0 0
T56 1 1 0 0
T59 1 1 0 0
T82 1 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2211100.00
CONT_ASSIGN4400
CONT_ASSIGN4911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
44 unreachable
49 1 1


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayLoadWidthCheck 2885 2885 0 0


PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 2885 2885 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T44 1 1 0 0
T45 1 1 0 0
T56 1 1 0 0
T59 1 1 0 0
T82 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%