Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender	87.50			87.50
tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50			87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50			87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.79	96.47	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.82	99.06	82.13	98.84		77.06	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.26	99.64	66.67	100.00		100.00	90.00	u_rv_plic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.79	96.47	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.79	96.47	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.79	96.47	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T57,T226,T160	Yes	T57,T226,T160	INPUT
alert_req_i	Yes	Yes	T174,T91,T115	Yes	T174,T79,T91	INPUT
alert_ack_o	Yes	Yes	T174,T79,T91	Yes	T174,T79,T91	OUTPUT
alert_state_o	Yes	Yes	T174,T91,T115	Yes	T174,T79,T91	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T57,T78,T226	Yes	T57,T78,T226	INPUT
alert_rx_i.ping_n	Yes	Yes	T78,T80,T269	Yes	T78,T80,T269	INPUT
alert_rx_i.ping_p	Yes	Yes	T78,T80,T269	Yes	T78,T80,T269	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T57,T78,T226	Yes	T57,T78,T226	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

	Total	Covered	Percent
Totals	12	10	83.33
Total Bits	24	21	87.50
Total Bits 0->1	12	11	91.67
Total Bits 1->0	12	10	83.33

Ports	12	10	83.33
Port Bits	24	21	87.50
Port Bits 0->1	12	11	91.67
Port Bits 1->0	12	10	83.33

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	INPUT
alert_req_i	Yes	Yes	T379	Yes	T379,T380	INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		Yes	T379	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T78,T80,T60	Yes	T78,T80,T60	INPUT
alert_rx_i.ping_n	Yes	Yes	T78,T80,T269	Yes	T80,T269,T81	INPUT
alert_rx_i.ping_p	Yes	Yes	T80,T269,T81	Yes	T78,T80,T269	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T78,T80,T60	Yes	T78,T80,T60	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T44,T17	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	INPUT
alert_req_i	Yes	Yes	T84,T85,T86	Yes	T79,T83,T84	INPUT
alert_ack_o	Yes	Yes	T79,T83,T84	Yes	T79,T83,T84	OUTPUT
alert_state_o	Yes	Yes	T84,T85,T86	Yes	T79,T83,T84	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_rx_i.ping_n	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_rx_i.ping_p	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	INPUT
alert_req_i	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	INPUT
alert_ack_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT
alert_state_o	Yes	Yes	T309,T310,T311	Yes	T309,T310,T311	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T78,T80,T60	Yes	T78,T80,T60	INPUT
alert_rx_i.ping_n	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_rx_i.ping_p	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T78,T80,T60	Yes	T78,T80,T60	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	INPUT
alert_req_i	Yes	Yes	T715,T716	Yes	T715,T716	INPUT
alert_ack_o	Yes	Yes	T715,T716	Yes	T715,T716	OUTPUT
alert_state_o	Yes	Yes	T715,T716	Yes	T715,T716	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T78,T80,T60	Yes	T78,T80,T60	INPUT
alert_rx_i.ping_n	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_rx_i.ping_p	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T78,T80,T60	Yes	T78,T80,T60	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T57,T226,T160	Yes	T57,T226,T160	INPUT
alert_req_i	Yes	Yes	T10	Yes	T10	INPUT
alert_ack_o	Yes	Yes	T10	Yes	T10	OUTPUT
alert_state_o	Yes	Yes	T10	Yes	T10	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T57,T78,T226	Yes	T57,T78,T226	INPUT
alert_rx_i.ping_n	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_rx_i.ping_p	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T57,T78,T226	Yes	T57,T78,T226	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	INPUT
alert_req_i	Yes	Yes	T174,T91,T115	Yes	T174,T91,T115	INPUT
alert_ack_o	Yes	Yes	T174,T91,T115	Yes	T174,T91,T115	OUTPUT
alert_state_o	Yes	Yes	T174,T91,T115	Yes	T174,T91,T115	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T78,T174,T91	Yes	T78,T174,T91	INPUT
alert_rx_i.ping_n	Yes	Yes	T78,T80,T81	Yes	T80,T81,T268	INPUT
alert_rx_i.ping_p	Yes	Yes	T80,T81,T268	Yes	T78,T80,T81	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T78,T174,T91	Yes	T78,T174,T91	OUTPUT