Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : clk_ctrl_and_main_pd_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_top_earlgrey_sva_0.1/clk_ctrl_and_main_pd_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.clk_ctrl_and_main_pd_sva_if 100.00 100.00



Module Instance : tb.dut.top_earlgrey.clk_ctrl_and_main_pd_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.60 90.68 90.10 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : clk_ctrl_and_main_pd_sva_if
TotalCoveredPercent
Totals 14 14 100.00
Total Bits 28 28 100.00
Total Bits 0->1 14 14 100.00
Total Bits 1->0 14 14 100.00

Ports 14 14 100.00
Port Bits 28 28 100.00
Port Bits 0->1 14 14 100.00
Port Bits 1->0 14 14 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_slow_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_slow_ni Yes Yes T5,T19,T20 Yes T4,T5,T6 INPUT
por_d0_ni Yes Yes T5,T6,T1 Yes T4,T5,T6 INPUT
core_clk_en Yes Yes T5,T6,T129 Yes T4,T5,T6 INPUT
core_clk_val Yes Yes T5,T6,T129 Yes T4,T5,T6 INPUT
clk_core_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
io_clk_en Yes Yes T5,T6,T129 Yes T4,T5,T6 INPUT
io_clk_val Yes Yes T5,T6,T129 Yes T4,T5,T6 INPUT
clk_io_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
usb_clk_en Yes Yes T5,T6,T18 Yes T4,T5,T6 INPUT
usb_clk_val Yes Yes T5,T6,T18 Yes T4,T5,T6 INPUT
clk_usb_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
main_pd_n Yes Yes T6,T1,T2 Yes T6,T1,T2 INPUT
main_pok Yes Yes T5,T6,T1 Yes T4,T5,T6 INPUT

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%