Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483268753	51812847	0	0
DepthKnown_A	483268753	483163346	0	0
RvalidKnown_A	483268753	483163346	0	0
WreadyKnown_A	483268753	483163346	0	0
gen_passthru_fifo.paramCheckPass	994	994	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	51812847	0	0
T4	134224	146219	0	0
T5	852105	101429	0	0
T6	127225	14887	0	0
T17	248399	31409	0	0
T18	153440	15536	0	0
T44	239702	237733	0	0
T45	138608	17032	0	0
T56	135405	146227	0	0
T59	38641	0	0	0
T82	80939	8711	0	0
T129	0	20122	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	483163346	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	483163346	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	483163346	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	994	994	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483268753	41217005	0	0
DepthKnown_A	483268753	483163346	0	0
RvalidKnown_A	483268753	483163346	0	0
WreadyKnown_A	483268753	483163346	0	0
gen_passthru_fifo.paramCheckPass	994	994	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	41217005	0	0
T4	134224	127995	0	0
T5	852105	85361	0	0
T6	127225	9730	0	0
T17	248399	22553	0	0
T18	153440	11901	0	0
T44	239702	232922	0	0
T45	138608	14684	0	0
T56	135405	128000	0	0
T59	38641	0	0	0
T82	80939	6444	0	0
T129	0	13567	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	483163346	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	483163346	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	483163346	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	994	994	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483268753	40108478	0	0
DepthKnown_A	483268753	483163346	0	0
RvalidKnown_A	483268753	483163346	0	0
WreadyKnown_A	483268753	483163346	0	0
gen_passthru_fifo.paramCheckPass	994	994	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	40108478	0	0
T4	134224	191256	0	0
T5	852105	147095	0	0
T6	127225	6602	0	0
T17	248399	16537	0	0
T18	153440	10867	0	0
T44	239702	62682	0	0
T45	138608	4824	0	0
T56	135405	201272	0	0
T59	38641	0	0	0
T82	80939	7557	0	0
T129	0	6633	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	483163346	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	483163346	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	483163346	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	994	994	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483268753	34503167	0	0
DepthKnown_A	483268753	483163346	0	0
RvalidKnown_A	483268753	483163346	0	0
WreadyKnown_A	483268753	483163346	0	0
gen_passthru_fifo.paramCheckPass	994	994	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	34503167	0	0
T4	134224	121857	0	0
T5	852105	78506	0	0
T6	127225	6306	0	0
T17	248399	16147	0	0
T18	153440	10688	0	0
T44	239702	61504	0	0
T45	138608	4655	0	0
T56	135405	121861	0	0
T59	38641	0	0	0
T82	80939	7198	0	0
T129	0	6363	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	483163346	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	483163346	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	483163346	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	994	994	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	555068904	95627	0	0
DepthKnown_A	555068904	554951198	0	0
RvalidKnown_A	555068904	554951198	0	0
WreadyKnown_A	555068904	554951198	0	0
gen_passthru_fifo.paramCheckPass	2885	2885	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	95627	0	0
T4	134224	36	0	0
T5	852105	27	0	0
T6	127225	30	0	0
T17	248399	151	0	0
T18	153440	15	0	0
T44	239702	61	0	0
T45	138608	47	0	0
T56	135405	36	0	0
T59	38641	0	0	0
T82	80939	14	0	0
T129	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2885	2885	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	555068904	97954	0	0
DepthKnown_A	555068904	554951198	0	0
RvalidKnown_A	555068904	554951198	0	0
WreadyKnown_A	555068904	554951198	0	0
gen_passthru_fifo.paramCheckPass	2885	2885	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	97954	0	0
T4	134224	36	0	0
T5	852105	27	0	0
T6	127225	30	0	0
T17	248399	151	0	0
T18	153440	15	0	0
T44	239702	61	0	0
T45	138608	47	0	0
T56	135405	36	0	0
T59	38641	0	0	0
T82	80939	14	0	0
T129	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2885	2885	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	555068904	49335	0	0
DepthKnown_A	555068904	554951198	0	0
RvalidKnown_A	555068904	554951198	0	0
WreadyKnown_A	555068904	554951198	0	0
gen_passthru_fifo.paramCheckPass	2885	2885	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	49335	0	0
T1	0	98	0	0
T4	134224	5	0	0
T5	852105	0	0	0
T6	127225	24	0	0
T17	248399	95	0	0
T18	153440	12	0	0
T44	239702	59	0	0
T45	138608	46	0	0
T56	135405	5	0	0
T59	38641	0	0	0
T82	80939	13	0	0
T129	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2885	2885	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	555068904	49335	0	0
DepthKnown_A	555068904	554951198	0	0
RvalidKnown_A	555068904	554951198	0	0
WreadyKnown_A	555068904	554951198	0	0
gen_passthru_fifo.paramCheckPass	2885	2885	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	49335	0	0
T1	0	98	0	0
T4	134224	5	0	0
T5	852105	0	0	0
T6	127225	24	0	0
T17	248399	95	0	0
T18	153440	12	0	0
T44	239702	59	0	0
T45	138608	46	0	0
T56	135405	5	0	0
T59	38641	0	0	0
T82	80939	13	0	0
T129	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2885	2885	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	555068904	46292	0	0
DepthKnown_A	555068904	554951198	0	0
RvalidKnown_A	555068904	554951198	0	0
WreadyKnown_A	555068904	554951198	0	0
gen_passthru_fifo.paramCheckPass	2885	2885	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	46292	0	0
T4	134224	31	0	0
T5	852105	27	0	0
T6	127225	6	0	0
T17	248399	56	0	0
T18	153440	3	0	0
T44	239702	2	0	0
T45	138608	1	0	0
T56	135405	31	0	0
T59	38641	0	0	0
T82	80939	1	0	0
T129	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2885	2885	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	555068904	48619	0	0
DepthKnown_A	555068904	554951198	0	0
RvalidKnown_A	555068904	554951198	0	0
WreadyKnown_A	555068904	554951198	0	0
gen_passthru_fifo.paramCheckPass	2885	2885	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	48619	0	0
T4	134224	31	0	0
T5	852105	27	0	0
T6	127225	6	0	0
T17	248399	56	0	0
T18	153440	3	0	0
T44	239702	2	0	0
T45	138608	1	0	0
T56	135405	31	0	0
T59	38641	0	0	0
T82	80939	1	0	0
T129	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555068904	554951198	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2885	2885	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0