Line Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 21 | 91.30 |
ALWAYS | 70 | 3 | 3 | 100.00 |
ALWAYS | 78 | 5 | 5 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 132 | 4 | 3 | 75.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 0 | 0.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
ALWAYS | 168 | 0 | 0 | |
ALWAYS | 178 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
73 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
82 |
1 |
1 |
84 |
1 |
1 |
|
|
|
MISSING_ELSE |
89 |
1 |
1 |
94 |
1 |
1 |
96 |
1 |
1 |
116 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
120 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
135 |
0 |
1 |
|
|
|
MISSING_ELSE |
141 |
1 |
1 |
145 |
1 |
1 |
149 |
0 |
1 |
153 |
1 |
1 |
168 |
|
unreachable |
170 |
|
unreachable |
171 |
|
unreachable |
172 |
|
unreachable |
173 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
178 |
|
unreachable |
179 |
|
unreachable |
181 |
|
unreachable |
Line Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 20 | 90.91 |
ALWAYS | 70 | 3 | 3 | 100.00 |
ALWAYS | 78 | 5 | 5 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
CONT_ASSIGN | 94 | 0 | 0 | |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 132 | 4 | 3 | 75.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 0 | 0.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
ALWAYS | 168 | 0 | 0 | |
ALWAYS | 178 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
73 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
82 |
1 |
1 |
84 |
1 |
1 |
|
|
|
MISSING_ELSE |
89 |
1 |
1 |
94 |
|
unreachable |
96 |
1 |
1 |
116 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
120 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
135 |
0 |
1 |
|
|
|
MISSING_ELSE |
141 |
1 |
1 |
145 |
1 |
1 |
149 |
0 |
1 |
153 |
1 |
1 |
168 |
|
unreachable |
170 |
|
unreachable |
171 |
|
unreachable |
172 |
|
unreachable |
173 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
178 |
|
unreachable |
179 |
|
unreachable |
181 |
|
unreachable |
Cond Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 13 | 9 | 69.23 |
Logical | 13 | 9 | 69.23 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 80
EXPRESSION (req_i && gnt_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T5,T6 |
LINE 81
EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
--------------------------------------------1-------------------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 94
EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Covered | T4,T5,T6 |
LINE 96
EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Covered | T4,T5,T6 |
LINE 96
SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Unreachable | |
LINE 141
EXPRESSION (tl_i.d_error | intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T221,T222,T54 |
LINE 145
EXPRESSION (intg_err_q | intg_err)
-----1---- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
Cond Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 17 | 14 | 82.35 |
Logical | 17 | 14 | 82.35 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 80
EXPRESSION (req_i && gnt_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T68,T76,T77 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T5,T6 |
LINE 81
EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
-----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 94
EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
----1----
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 96
EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
----1----
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 96
SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
----1----
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 141
EXPRESSION (tl_i.d_error | intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T64,T223,T224 |
LINE 145
EXPRESSION (intg_err_q | intg_err)
-----1---- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
Branch Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
9 |
90.00 |
TERNARY |
94 |
2 |
2 |
100.00 |
IF |
132 |
3 |
2 |
66.67 |
IF |
70 |
2 |
2 |
100.00 |
IF |
80 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 94 ((~we_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 132 if ((!rst_ni))
-2-: 134 if (intg_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 80 if ((req_i && gnt_o))
-2-: 81 if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T4,T5,T6 |
1 |
0 |
Covered |
T4,T5,T6 |
0 |
- |
Covered |
T4,T5,T6 |
Branch Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
8 |
88.89 |
TERNARY |
94 |
1 |
1 |
100.00 |
IF |
132 |
3 |
2 |
66.67 |
IF |
70 |
2 |
2 |
100.00 |
IF |
80 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 94 ((~we_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Unreachable |
|
LineNo. Expression
-1-: 132 if ((!rst_ni))
-2-: 134 if (intg_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 80 if ((req_i && gnt_o))
-2-: 81 if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0]))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T4,T5,T6 |
1 |
0 |
Covered |
T4,T5,T6 |
0 |
- |
Covered |
T4,T5,T6 |
Assert Coverage for Module :
tlul_adapter_host
Assertion Details
DontExceeedMaxReqs
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
966537506 |
91877488 |
0 |
0 |
T4 |
268448 |
337475 |
0 |
0 |
T5 |
1704210 |
248524 |
0 |
0 |
T6 |
254450 |
21489 |
0 |
0 |
T17 |
496798 |
47946 |
0 |
0 |
T18 |
306880 |
26403 |
0 |
0 |
T44 |
479404 |
300415 |
0 |
0 |
T45 |
277216 |
21856 |
0 |
0 |
T56 |
270810 |
347499 |
0 |
0 |
T59 |
77282 |
0 |
0 |
0 |
T82 |
161878 |
16268 |
0 |
0 |
T129 |
0 |
26755 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 20 | 90.91 |
ALWAYS | 70 | 3 | 3 | 100.00 |
ALWAYS | 78 | 5 | 5 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
CONT_ASSIGN | 94 | 0 | 0 | |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 132 | 4 | 3 | 75.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 0 | 0.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
ALWAYS | 168 | 0 | 0 | |
ALWAYS | 178 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
73 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
82 |
1 |
1 |
84 |
1 |
1 |
|
|
|
MISSING_ELSE |
89 |
1 |
1 |
94 |
|
unreachable |
96 |
1 |
1 |
116 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
120 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
135 |
0 |
1 |
|
|
|
MISSING_ELSE |
141 |
1 |
1 |
145 |
1 |
1 |
149 |
0 |
1 |
153 |
1 |
1 |
168 |
|
unreachable |
170 |
|
unreachable |
171 |
|
unreachable |
172 |
|
unreachable |
173 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
178 |
|
unreachable |
179 |
|
unreachable |
181 |
|
unreachable |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
| Total | Covered | Percent |
Conditions | 13 | 9 | 69.23 |
Logical | 13 | 9 | 69.23 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 80
EXPRESSION (req_i && gnt_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T5,T6 |
LINE 81
EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
--------------------------------------------1-------------------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 94
EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Covered | T4,T5,T6 |
LINE 96
EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Covered | T4,T5,T6 |
LINE 96
SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Unreachable | |
LINE 141
EXPRESSION (tl_i.d_error | intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T221,T222,T54 |
LINE 145
EXPRESSION (intg_err_q | intg_err)
-----1---- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
8 |
88.89 |
TERNARY |
94 |
1 |
1 |
100.00 |
IF |
132 |
3 |
2 |
66.67 |
IF |
70 |
2 |
2 |
100.00 |
IF |
80 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 94 ((~we_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Unreachable |
|
LineNo. Expression
-1-: 132 if ((!rst_ni))
-2-: 134 if (intg_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 80 if ((req_i && gnt_o))
-2-: 81 if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0]))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T4,T5,T6 |
1 |
0 |
Covered |
T4,T5,T6 |
0 |
- |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
Assertion Details
DontExceeedMaxReqs
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483268753 |
51812847 |
0 |
0 |
T4 |
134224 |
146219 |
0 |
0 |
T5 |
852105 |
101429 |
0 |
0 |
T6 |
127225 |
14887 |
0 |
0 |
T17 |
248399 |
31409 |
0 |
0 |
T18 |
153440 |
15536 |
0 |
0 |
T44 |
239702 |
237733 |
0 |
0 |
T45 |
138608 |
17032 |
0 |
0 |
T56 |
135405 |
146227 |
0 |
0 |
T59 |
38641 |
0 |
0 |
0 |
T82 |
80939 |
8711 |
0 |
0 |
T129 |
0 |
20122 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 21 | 91.30 |
ALWAYS | 70 | 3 | 3 | 100.00 |
ALWAYS | 78 | 5 | 5 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 132 | 4 | 3 | 75.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 0 | 0.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
ALWAYS | 168 | 0 | 0 | |
ALWAYS | 178 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
73 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
82 |
1 |
1 |
84 |
1 |
1 |
|
|
|
MISSING_ELSE |
89 |
1 |
1 |
94 |
1 |
1 |
96 |
1 |
1 |
116 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
120 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
135 |
0 |
1 |
|
|
|
MISSING_ELSE |
141 |
1 |
1 |
145 |
1 |
1 |
149 |
0 |
1 |
153 |
1 |
1 |
168 |
|
unreachable |
170 |
|
unreachable |
171 |
|
unreachable |
172 |
|
unreachable |
173 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
178 |
|
unreachable |
179 |
|
unreachable |
181 |
|
unreachable |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
| Total | Covered | Percent |
Conditions | 17 | 14 | 82.35 |
Logical | 17 | 14 | 82.35 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 80
EXPRESSION (req_i && gnt_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T68,T76,T77 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T5,T6 |
LINE 81
EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
-----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 94
EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
----1----
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 96
EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
----1----
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 96
SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
----1----
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 141
EXPRESSION (tl_i.d_error | intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T64,T223,T224 |
LINE 145
EXPRESSION (intg_err_q | intg_err)
-----1---- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
9 |
90.00 |
TERNARY |
94 |
2 |
2 |
100.00 |
IF |
132 |
3 |
2 |
66.67 |
IF |
70 |
2 |
2 |
100.00 |
IF |
80 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 94 ((~we_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 132 if ((!rst_ni))
-2-: 134 if (intg_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 80 if ((req_i && gnt_o))
-2-: 81 if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T4,T5,T6 |
1 |
0 |
Covered |
T4,T5,T6 |
0 |
- |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
Assertion Details
DontExceeedMaxReqs
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483268753 |
40064641 |
0 |
0 |
T4 |
134224 |
191256 |
0 |
0 |
T5 |
852105 |
147095 |
0 |
0 |
T6 |
127225 |
6602 |
0 |
0 |
T17 |
248399 |
16537 |
0 |
0 |
T18 |
153440 |
10867 |
0 |
0 |
T44 |
239702 |
62682 |
0 |
0 |
T45 |
138608 |
4824 |
0 |
0 |
T56 |
135405 |
201272 |
0 |
0 |
T59 |
38641 |
0 |
0 |
0 |
T82 |
80939 |
7557 |
0 |
0 |
T129 |
0 |
6633 |
0 |
0 |