Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T68,*T76,*T77	Yes	T68,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T76,T77	Yes	T68,T76,T77	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T104,T211	Yes	T5,T104,T211	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T104,T211	Yes	T4,T5,T56	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T104,T211	Yes	T4,T5,T56	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T149,*T74,*T75	Yes	T149,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T104,*T211	Yes	T5,T104,T211	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T749,T160	Yes	T78,T749,T160	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T80,T249	Yes	T78,T80,T249	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T80,T249	Yes	T78,T80,T249	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T749,T160	Yes	T78,T749,T160	OUTPUT
cio_rx_i	Yes	Yes	T5,T44,T17	Yes	T5,T6,T45	INPUT
cio_tx_o	Yes	Yes	T5,T104,T211	Yes	T5,T104,T211	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T104,T211,T207	Yes	T104,T211,T207	OUTPUT
intr_rx_watermark_o	Yes	Yes	T104,T211,T207	Yes	T104,T211,T207	OUTPUT
intr_tx_empty_o	Yes	Yes	T104,T211,T207	Yes	T104,T211,T207	OUTPUT
intr_rx_overflow_o	Yes	Yes	T104,T211,T207	Yes	T104,T211,T207	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT
intr_rx_break_err_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT
intr_rx_timeout_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T68,*T76,*T77	Yes	T68,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T76,T77	Yes	T68,T76,T77	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_o.d_error	Yes	Yes	T74,T75,T127	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T54,T55	Yes	T5,T54,T55	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T54,T55	Yes	T4,T5,T56	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T54,T55	Yes	T4,T5,T56	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T149,*T74,*T75	Yes	T149,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T54,*T55	Yes	T5,T54,T55	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T160,T80	Yes	T78,T160,T80	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T160,T80	Yes	T78,T160,T80	OUTPUT
cio_rx_i	Yes	Yes	T5,T44,T17	Yes	T5,T6,T45	INPUT
cio_tx_o	Yes	Yes	T5,T54,T55	Yes	T5,T54,T55	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T308,T217,T218	Yes	T308,T217,T218	OUTPUT
intr_rx_watermark_o	Yes	Yes	T308,T217,T218	Yes	T308,T217,T218	OUTPUT
intr_tx_empty_o	Yes	Yes	T308,T217,T218	Yes	T308,T217,T218	OUTPUT
intr_rx_overflow_o	Yes	Yes	T308,T217,T218	Yes	T308,T217,T218	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT
intr_rx_break_err_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT
intr_rx_timeout_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T211,T308,T212	Yes	T211,T308,T212	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T211,T308,T212	Yes	T211,T308,T212	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T68,*T76,*T77	Yes	T68,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T76,T77	Yes	T68,T76,T77	INPUT
tl_i.a_valid	Yes	Yes	T211,T308,T212	Yes	T211,T308,T212	INPUT
tl_o.a_ready	Yes	Yes	T211,T308,T212	Yes	T211,T308,T212	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T127	Yes	T73,T74,T127	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T211,T308,T212	Yes	T211,T308,T212	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T211,T308,T212	Yes	T211,T308,T212	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T211,T308,T212	Yes	T211,T308,T212	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T74,T75,T127	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T149,*T74,*T75	Yes	T149,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T211,*T308,*T212	Yes	T211,T308,T212	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T211,T308,T212	Yes	T211,T308,T212	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T160,T80	Yes	T78,T160,T80	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T160,T80	Yes	T78,T160,T80	OUTPUT
cio_rx_i	Yes	Yes	T46,T211,T212	Yes	T46,T211,T25	INPUT
cio_tx_o	Yes	Yes	T211,T212,T328	Yes	T211,T212,T328	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T211,T308,T212	Yes	T211,T308,T212	OUTPUT
intr_rx_watermark_o	Yes	Yes	T211,T308,T212	Yes	T211,T308,T212	OUTPUT
intr_tx_empty_o	Yes	Yes	T211,T308,T212	Yes	T211,T308,T212	OUTPUT
intr_rx_overflow_o	Yes	Yes	T211,T308,T212	Yes	T211,T308,T212	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT
intr_rx_break_err_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT
intr_rx_timeout_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T104,T207,T332	Yes	T104,T207,T332	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T104,T207,T332	Yes	T104,T207,T332	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T68,*T76,*T77	Yes	T68,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T76,T77	Yes	T68,T76,T77	INPUT
tl_i.a_valid	Yes	Yes	T104,T207,T332	Yes	T104,T207,T332	INPUT
tl_o.a_ready	Yes	Yes	T104,T207,T332	Yes	T104,T207,T332	OUTPUT
tl_o.d_error	Yes	Yes	T74,T75,T127	Yes	T74,T75,T127	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T104,T207,T332	Yes	T104,T207,T332	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T104,T207,T332	Yes	T104,T207,T332	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T104,T207,T332	Yes	T104,T207,T332	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T149,*T74,*T75	Yes	T149,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T104,*T207,*T332	Yes	T104,T207,T332	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T104,T207,T332	Yes	T104,T207,T332	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T160,T80	Yes	T78,T160,T80	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T80,T249	Yes	T78,T80,T249	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T80,T249	Yes	T78,T80,T249	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T160,T80	Yes	T78,T160,T80	OUTPUT
cio_rx_i	Yes	Yes	T104,T207,T332	Yes	T104,T207,T332	INPUT
cio_tx_o	Yes	Yes	T104,T207,T332	Yes	T104,T207,T332	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T104,T207,T332	Yes	T104,T207,T332	OUTPUT
intr_rx_watermark_o	Yes	Yes	T104,T207,T332	Yes	T104,T207,T332	OUTPUT
intr_tx_empty_o	Yes	Yes	T104,T207,T332	Yes	T104,T207,T332	OUTPUT
intr_rx_overflow_o	Yes	Yes	T104,T207,T332	Yes	T104,T207,T332	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT
intr_rx_break_err_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT
intr_rx_timeout_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T27,T28,T308	Yes	T27,T28,T308	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T27,T28,T308	Yes	T27,T28,T308	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T68,*T76,*T77	Yes	T68,T76,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T76,T77	Yes	T68,T76,T77	INPUT
tl_i.a_valid	Yes	Yes	T27,T28,T308	Yes	T27,T28,T308	INPUT
tl_o.a_ready	Yes	Yes	T27,T28,T308	Yes	T27,T28,T308	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T127	Yes	T73,T74,T127	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T27,T28,T308	Yes	T27,T28,T308	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T27,T28,T308	Yes	T27,T28,T308	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T27,T28,T308	Yes	T27,T28,T308	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T149,*T74,*T75	Yes	T149,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T27,*T28,*T308	Yes	T27,T28,T308	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T27,T28,T308	Yes	T27,T28,T308	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T749,T160	Yes	T78,T749,T160	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T749,T160	Yes	T78,T749,T160	OUTPUT
cio_rx_i	Yes	Yes	T27,T28,T304	Yes	T27,T28,T304	INPUT
cio_tx_o	Yes	Yes	T27,T28,T304	Yes	T27,T28,T304	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T27,T28,T308	Yes	T27,T28,T308	OUTPUT
intr_rx_watermark_o	Yes	Yes	T27,T28,T308	Yes	T27,T28,T308	OUTPUT
intr_tx_empty_o	Yes	Yes	T27,T28,T308	Yes	T27,T28,T308	OUTPUT
intr_rx_overflow_o	Yes	Yes	T27,T28,T308	Yes	T27,T28,T308	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT
intr_rx_break_err_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT
intr_rx_timeout_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T308,T334,T335	Yes	T308,T334,T335	OUTPUT

*Tests covering at least one bit in the range