Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_por_aon_n_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T46,T24,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T46,T24,T25
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T46,T24,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	26077	25711	0	0
selKnown1	28029	26756	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	26077	25711	0	0
T19	3	2	0	0
T21	1	0	0	0
T23	1	0	0	0
T24	2446	2444	0	0
T25	100	98	0	0
T26	5318	5316	0	0
T29	4	3	0	0
T41	19	17	0	0
T42	11	11	0	0
T43	0	24	0	0
T57	2	1	0	0
T58	16	15	0	0
T63	3	2	0	0
T68	0	1	0	0
T69	0	24	0	0
T118	6	5	0	0
T119	1	0	0	0
T165	1	0	0	0
T166	3	2	0	0
T184	0	2	0	0
T185	3218	3216	0	0
T186	2962	2960	0	0
T187	3529	3527	0	0
T188	3028	3026	0	0
T189	0	4	0	0
T190	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	28029	26756	0	0
T5	2	1	0	0
T6	1	0	0	0
T17	2	1	0	0
T18	1	0	0	0
T19	0	2	0	0
T20	0	10	0	0
T41	28	26	0	0
T42	18	16	0	0
T43	5	10	0	0
T44	2	1	0	0
T45	1	0	0	0
T46	545	544	0	0
T56	1	0	0	0
T57	0	1	0	0
T58	0	16	0	0
T59	1	0	0	0
T64	0	4	0	0
T82	1	0	0	0
T125	0	1	0	0
T126	0	1	0	0
T129	1	0	0	0
T189	15	26	0	0
T191	9	15	0	0
T192	3	5	0	0
T193	18	35	0	0
T194	15	24	0	0
T195	7	6	0	0
T196	7	6	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T46,T24,T26
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	1202	1184	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202	1184	0	0
T24	1	0	0	0
T26	1	0	0	0
T41	15	14	0	0
T42	10	9	0	0
T43	0	6	0	0
T46	545	544	0	0
T47	545	544	0	0
T185	1	0	0	0
T186	1	0	0	0
T187	1	0	0	0
T188	1	0	0	0
T189	0	12	0	0
T191	0	7	0	0
T192	0	3	0	0
T193	0	18	0	0
T194	0	10	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T46,T47,T22
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	104	90	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	90	0	0
T41	13	12	0	0
T42	8	7	0	0
T43	5	4	0	0
T189	15	14	0	0
T191	9	8	0	0
T192	3	2	0	0
T193	18	17	0	0
T194	15	14	0	0
T195	7	6	0	0
T196	7	6	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T46,T25,T47
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	132	119	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	132	119	0	0
T25	1	0	0	0
T41	10	9	0	0
T42	12	11	0	0
T43	7	6	0	0
T46	2	1	0	0
T47	2	1	0	0
T189	13	12	0	0
T191	10	9	0	0
T192	11	10	0	0
T193	26	25	0	0
T194	0	14	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T46,T21,T47
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	108	94	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	108	94	0	0
T41	8	7	0	0
T42	11	10	0	0
T43	7	6	0	0
T189	13	12	0	0
T191	8	7	0	0
T192	9	8	0	0
T193	15	14	0	0
T194	15	14	0	0
T195	11	10	0	0
T196	7	6	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T41,T42
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	126	115	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	126	115	0	0
T41	9	8	0	0
T42	20	19	0	0
T43	8	7	0	0
T189	12	11	0	0
T191	13	12	0	0
T192	7	6	0	0
T193	7	6	0	0
T194	27	26	0	0
T195	14	13	0	0
T196	8	7	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T41
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	93	81	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	93	81	0	0
T41	8	7	0	0
T42	14	13	0	0
T43	2	1	0	0
T189	10	9	0	0
T191	10	9	0	0
T192	8	7	0	0
T193	8	7	0	0
T194	21	20	0	0
T195	6	5	0	0
T196	4	3	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T59,T19,T57
0	1	Covered	T59,T19,T57
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T19,T57
1	1	Covered	T59,T19,T57

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	975	853	0	0
selKnown1	1738	754	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	853	0	0
T19	3	2	0	0
T29	4	3	0	0
T57	2	1	0	0
T58	16	15	0	0
T63	3	2	0	0
T68	0	1	0	0
T69	0	24	0	0
T118	6	5	0	0
T119	1	0	0	0
T165	1	0	0	0
T166	3	2	0	0
T184	0	2	0	0
T190	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1738	754	0	0
T5	2	1	0	0
T6	1	0	0	0
T17	2	1	0	0
T18	1	0	0	0
T19	0	2	0	0
T20	0	10	0	0
T44	2	1	0	0
T45	1	0	0	0
T56	1	0	0	0
T57	0	1	0	0
T58	0	16	0	0
T59	1	0	0	0
T64	0	4	0	0
T82	1	0	0	0
T125	0	1	0	0
T126	0	1	0	0
T129	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T25,T26
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T46,T47,T22
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T24,T25,T26

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20476	20459	0	0
selKnown1	419	405	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20476	20459	0	0
T24	2372	2371	0	0
T25	99	98	0	0
T26	5305	5304	0	0
T41	12	11	0	0
T42	11	10	0	0
T43	17	16	0	0
T185	3142	3141	0	0
T186	2946	2945	0	0
T187	3510	3509	0	0
T188	2953	2952	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	419	405	0	0
T22	1	0	0	0
T23	1	0	0	0
T41	11	10	0	0
T42	5	4	0	0
T43	10	9	0	0
T46	143	142	0	0
T47	161	160	0	0
T189	17	16	0	0
T191	11	10	0	0
T192	4	3	0	0
T193	0	18	0	0
T194	0	9	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T25,T21
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T46,T21,T47
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T24,T25,T21

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	333	314	0	0
selKnown1	111	96	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	333	314	0	0
T21	1	0	0	0
T23	1	0	0	0
T24	74	73	0	0
T25	1	0	0	0
T26	13	12	0	0
T41	7	6	0	0
T42	0	1	0	0
T43	0	8	0	0
T185	76	75	0	0
T186	16	15	0	0
T187	19	18	0	0
T188	75	74	0	0
T189	0	4	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	111	96	0	0
T41	9	8	0	0
T42	5	4	0	0
T43	11	10	0	0
T189	13	12	0	0
T191	8	7	0	0
T192	6	5	0	0
T193	16	15	0	0
T194	12	11	0	0
T195	21	20	0	0
T196	5	4	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T46,T68,T21
0	1	Covered	T46,T25,T21
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T46,T68,T21
1	1	Covered	T46,T25,T21

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1254	1234	0	0
selKnown1	54	33	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254	1234	0	0
T10	1	0	0	0
T21	1	0	0	0
T25	1	0	0	0
T41	0	11	0	0
T42	0	16	0	0
T43	0	13	0	0
T46	546	545	0	0
T47	546	545	0	0
T68	1	0	0	0
T76	1	0	0	0
T77	1	0	0	0
T149	1	0	0	0
T189	0	17	0	0
T191	0	14	0	0
T192	0	6	0	0
T193	0	16	0	0
T194	0	10	0	0
T197	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	54	33	0	0
T21	2	1	0	0
T22	2	1	0	0
T23	2	1	0	0
T35	1	0	0	0
T36	1	0	0	0
T37	1	0	0	0
T41	0	3	0	0
T42	0	3	0	0
T43	0	3	0	0
T72	1	0	0	0
T189	0	3	0	0
T191	0	3	0	0
T192	0	3	0	0
T193	0	3	0	0
T198	1	0	0	0
T199	1	0	0	0
T200	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T46,T68,T21
0	1	Covered	T46,T25,T21
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T46,T68,T21
1	1	Covered	T46,T25,T21

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1256	1236	0	0
selKnown1	54	33	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1256	1236	0	0
T10	1	0	0	0
T21	1	0	0	0
T25	1	0	0	0
T41	0	12	0	0
T42	0	17	0	0
T43	0	12	0	0
T46	546	545	0	0
T47	546	545	0	0
T68	1	0	0	0
T76	1	0	0	0
T77	1	0	0	0
T149	1	0	0	0
T189	0	17	0	0
T191	0	16	0	0
T192	0	6	0	0
T193	0	16	0	0
T194	0	11	0	0
T197	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	54	33	0	0
T21	2	1	0	0
T22	2	1	0	0
T23	2	1	0	0
T35	1	0	0	0
T36	1	0	0	0
T37	1	0	0	0
T41	0	3	0	0
T42	0	3	0	0
T43	0	3	0	0
T72	1	0	0	0
T189	0	3	0	0
T191	0	3	0	0
T192	0	3	0	0
T193	0	3	0	0
T198	1	0	0	0
T199	1	0	0	0
T200	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T46,T68,T3
0	1	Covered	T46,T24,T3
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T46,T68,T3
1	1	Covered	T46,T24,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	166	139	0	0
selKnown1	24	3	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	166	139	0	0
T3	1	0	0	0
T24	1	0	0	0
T25	1	0	0	0
T26	1	0	0	0
T41	0	19	0	0
T42	0	9	0	0
T43	0	15	0	0
T46	2	1	0	0
T47	0	1	0	0
T68	1	0	0	0
T76	1	0	0	0
T77	1	0	0	0
T185	1	0	0	0
T189	0	16	0	0
T191	0	15	0	0
T192	0	13	0	0
T193	0	13	0	0
T194	0	6	0	0
T197	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	24	3	0	0
T21	2	1	0	0
T22	2	1	0	0
T23	2	1	0	0
T35	1	0	0	0
T36	1	0	0	0
T37	1	0	0	0
T72	1	0	0	0
T198	1	0	0	0
T199	1	0	0	0
T200	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T46,T68,T3
0	1	Covered	T46,T24,T3
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T46,T68,T3
1	1	Covered	T46,T24,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	171	144	0	0
selKnown1	24	3	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	171	144	0	0
T3	1	0	0	0
T24	1	0	0	0
T25	1	0	0	0
T26	1	0	0	0
T41	0	20	0	0
T42	0	8	0	0
T43	0	15	0	0
T46	2	1	0	0
T47	0	1	0	0
T68	1	0	0	0
T76	1	0	0	0
T77	1	0	0	0
T185	1	0	0	0
T189	0	17	0	0
T191	0	16	0	0
T192	0	13	0	0
T193	0	14	0	0
T194	0	8	0	0
T197	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	24	3	0	0
T21	2	1	0	0
T22	2	1	0	0
T23	2	1	0	0
T35	1	0	0	0
T36	1	0	0	0
T37	1	0	0	0
T72	1	0	0	0
T198	1	0	0	0
T199	1	0	0	0
T200	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T68,T76,T77
0	1	Covered	T21,T23,T41
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T68,T76,T77
1	1	Covered	T21,T23,T41

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	144	126	0	0
selKnown1	24	3	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	144	126	0	0
T41	6	5	0	0
T42	14	13	0	0
T43	14	13	0	0
T189	9	8	0	0
T191	9	8	0	0
T192	14	13	0	0
T193	13	12	0	0
T194	19	18	0	0
T195	22	21	0	0
T196	16	15	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	24	3	0	0
T21	2	1	0	0
T22	2	1	0	0
T23	2	1	0	0
T35	1	0	0	0
T36	1	0	0	0
T37	1	0	0	0
T72	1	0	0	0
T198	1	0	0	0
T199	1	0	0	0
T200	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T68,T76,T77
0	1	Covered	T21,T23,T41
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T68,T76,T77
1	1	Covered	T21,T23,T41

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	145	127	0	0
selKnown1	24	3	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	145	127	0	0
T41	6	5	0	0
T42	15	14	0	0
T43	14	13	0	0
T189	8	7	0	0
T191	10	9	0	0
T192	15	14	0	0
T193	14	13	0	0
T194	18	17	0	0
T195	21	20	0	0
T196	16	15	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	24	3	0	0
T21	2	1	0	0
T22	2	1	0	0
T23	2	1	0	0
T35	1	0	0	0
T36	1	0	0	0
T37	1	0	0	0
T72	1	0	0	0
T198	1	0	0	0
T199	1	0	0	0
T200	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T46,T68,T201
0	1	Covered	T46,T24,T25
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T46,T24,T25
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T46,T68,T201
1	1	Covered	T46,T24,T25

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	582	543	0	0
selKnown1	11899	11873	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	582	543	0	0
T24	1	0	0	0
T25	1	0	0	0
T26	1	0	0	0
T32	2	1	0	0
T33	2	1	0	0
T46	137	136	0	0
T47	0	155	0	0
T68	1	0	0	0
T201	31	30	0	0
T202	2	1	0	0
T203	24	23	0	0
T204	0	30	0	0
T205	0	1	0	0
T206	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	11899	11873	0	0
T10	1	0	0	0
T24	1575	1574	0	0
T25	96	95	0	0
T26	5280	5279	0	0
T41	0	10	0	0
T42	0	11	0	0
T43	0	15	0	0
T47	1	0	0	0
T68	1	0	0	0
T76	1	0	0	0
T77	1	0	0	0
T185	2037	2036	0	0
T186	0	52	0	0
T187	0	855	0	0
T188	0	1860	0	0
T197	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T46,T68,T201
0	1	Covered	T46,T24,T25
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T46,T24,T25
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T46,T68,T201
1	1	Covered	T46,T24,T25

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	575	536	0	0
selKnown1	11893	11867	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	575	536	0	0
T24	1	0	0	0
T25	1	0	0	0
T26	1	0	0	0
T32	2	1	0	0
T33	2	1	0	0
T46	137	136	0	0
T47	0	155	0	0
T68	1	0	0	0
T201	31	30	0	0
T202	2	1	0	0
T203	24	23	0	0
T204	0	30	0	0
T205	0	1	0	0
T206	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	11893	11867	0	0
T10	1	0	0	0
T24	1575	1574	0	0
T25	96	95	0	0
T26	5280	5279	0	0
T41	0	10	0	0
T42	0	11	0	0
T43	0	15	0	0
T47	1	0	0	0
T68	1	0	0	0
T76	1	0	0	0
T77	1	0	0	0
T185	2037	2036	0	0
T186	0	52	0	0
T187	0	855	0	0
T188	0	1860	0	0
T197	1	0	0	0