Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T75,T127,T128	Yes	T75,T127,T128	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T221,T222,T54	Yes	T221,T222,T54	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T221,T222,T54	Yes	T221,T222,T54	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T68,T76,T77	Yes	T68,T76,T77	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T77,T10,T149	Yes	T77,T10,T149	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T77,T10,T149	Yes	T77,T10,T149	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T64,T223,T224	Yes	T64,T223,T224	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T10,T73,T74	Yes	T10,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T10,T73,T74	Yes	T10,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T10,T73,T74	Yes	T10,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T10,T73,T74	Yes	T10,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T10,T73,T74	Yes	T10,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T10,T73,T74	Yes	T10,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T74,T75,T127	Yes	T74,T75,T127	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T10,T73,T74	Yes	T10,T73,T74	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T10,T73,T74	Yes	T10,T73,T74	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T10,T74,T75	Yes	T10,T73,T74	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T10,T73,T74	Yes	T10,T73,T74	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T10,T73,T74	Yes	T10,T73,T74	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T10,T74,T75	Yes	T10,T73,T74	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T74,T75,T127	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T10,*T73,*T74	Yes	T10,T73,T74	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T10,T73,T74	Yes	T10,T73,T74	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T10,T262,T263	Yes	T10,T262,T263	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T10,T262,T263	Yes	T10,T262,T263	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T10,T262,T263	Yes	T10,T262,T263	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T10,T262,T263	Yes	T10,T262,T263	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T10,T262,T263	Yes	T10,T262,T263	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T262,*T263,*T264	Yes	T262,T263,T264	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T10,T262,T263	Yes	T10,T262,T263	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T44	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T262,T263,T264	Yes	T262,T263,T264	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T10,T262,T263	Yes	T10,T262,T263	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T6,T44	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T262,*T263,*T264	Yes	T262,T263,T264	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T5,T6,T44	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T10,T262,T263	Yes	T10,T262,T263	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T20,T68,T147	Yes	T20,T68,T147	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T299,T431	Yes	T60,T299,T431	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T60,T299,T431	Yes	T60,T299,T431	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T60,T299,T431	Yes	T60,T299,T431	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T10,*T73,*T74	Yes	T10,T73,T74	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T60,T299,T431	Yes	T60,T299,T431	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T60,T299,T431	Yes	T60,T299,T431	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T432,T433,T434	Yes	T432,T433,T434	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T10,T73,T74	Yes	T60,T61,T62	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T432,T433,T434	Yes	T60,T432,T61	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T10,T74,*T75	Yes	T10,T73,T74	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T299,*T431,*T433	Yes	T299,T431,T432	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T60,T299,T431	Yes	T60,T299,T431	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T68,*T76,*T77	Yes	T68,T76,T77	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T68,T76,T77	Yes	T68,T76,T77	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T17,T223,T337	Yes	T17,T223,T337	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T68,*T76,*T77	Yes	T68,T76,T77	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T24,T25,T156	Yes	T24,T25,T156	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T24,T25,T156	Yes	T24,T25,T156	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T24,T25,T156	Yes	T24,T25,T156	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T24,T25,T156	Yes	T24,T25,T156	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T24,T25,T156	Yes	T24,T25,T156	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T24,T25,T156	Yes	T24,T25,T156	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T24,T185,T188	Yes	T24,T185,T188	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T24,T25,T156	Yes	T24,T25,T156	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T24,T25,T156	Yes	T24,T25,T156	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T24,T25,T156	Yes	T24,T25,T156	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T24,T25,T156	Yes	T24,T25,T156	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T24,T25,T156	Yes	T24,T25,T156	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T24,*T25,*T156	Yes	T24,T25,T156	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T24,T25,T156	Yes	T24,T25,T156	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T46,T156,T60	Yes	T46,T156,T60	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T46,T156,T60	Yes	T46,T156,T60	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T46,T156,T60	Yes	T46,T156,T60	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T46,T156,T60	Yes	T46,T156,T60	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T46,T156,T60	Yes	T46,T156,T60	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T46,T156,T60	Yes	T46,T156,T60	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T46,T156,T60	Yes	T46,T156,T60	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T46,T156,T60	Yes	T46,T156,T60	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T74,T75,T127	Yes	T73,T74,T75	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T46,T156,T382	Yes	T46,T156,T382	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T46,T156,T382	Yes	T46,T156,T60	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T46,T156,T382	Yes	T46,T156,T382	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T74,T75,T127	Yes	T73,T74,T75	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T74,*T75,*T127	Yes	T73,T74,T75	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T74,T75,T127	Yes	T73,T74,T75	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T46,*T156,*T382	Yes	T46,T156,T382	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T46,T156,T60	Yes	T46,T156,T60	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T1,T2,T30	Yes	T1,T2,T30	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T30	Yes	T1,T2,T30	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T30	Yes	T1,T2,T30	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T30	Yes	T1,T2,T30	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T1,T2,T30	Yes	T1,T2,T30	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T1,T2,T30	Yes	T1,T2,T30	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T149,*T74,*T75	Yes	T149,T74,T75	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T74,T75,T127	Yes	T74,T75,T127	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T1,T2,T30	Yes	T1,T2,T30	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T1,T2,T30	Yes	T1,T2,T30	INPUT
tl_usbdev_i.d_error	Yes	Yes	T74,T127,T128	Yes	T73,T74,T127	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T31,T308,T35	Yes	T31,T308,T35	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T30,T31,T308	Yes	T30,T31,T308	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T1,T2,T30	Yes	T1,T2,T31	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T74,T75,T127	Yes	T73,T74,T75	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T149,*T74,*T127	Yes	T149,T74,T127	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T74,T75,T127	Yes	T74,T75,T127	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T30	Yes	T1,T2,T31	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T1,T2,T30	Yes	T1,T2,T30	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T76,*T73,*T74	Yes	T76,T73,T74	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T44	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T76,*T74,*T75	Yes	T76,T73,T74	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T76,T73,T74	Yes	T76,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T76,T73,T74	Yes	T76,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T76,T73,T74	Yes	T76,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T76,T73,T74	Yes	T76,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T76,T73,T74	Yes	T76,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T76,T73,T74	Yes	T76,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T76,T73,T74	Yes	T76,T73,T74	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T76,T73,T74	Yes	T76,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T76,T73,T74	Yes	T76,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T76,T73,T74	Yes	T76,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T76,T73,T74	Yes	T76,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T76,T74,T75	Yes	T76,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T76,*T73,*T74	Yes	T76,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T76,T73,T74	Yes	T76,T73,T74	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T5,T44	Yes	T4,T5,T44	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T44	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_hmac_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T76,*T73,*T74	Yes	T76,T73,T74	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T737,T738,T349	Yes	T737,T738,T349	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_hmac_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_hmac_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T76,*T74,*T75	Yes	T76,T73,T74	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T56	Yes	T4,T5,T56	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_kmac_o.d_ready	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T82,T125,T126	Yes	T82,T125,T126	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T17,T82,T125	Yes	T17,T82,T125	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T17,T82,T125	Yes	T17,T82,T125	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T82,T125,T126	Yes	T82,T125,T126	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T17,T82,T125	Yes	T17,T82,T125	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T76,*T74,*T75	Yes	T76,T74,T75	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T82,T438,T225	Yes	T82,T438,T225	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T17,T82,T125	Yes	T17,T82,T125	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T17,T82,T125	Yes	T17,T82,T125	INPUT
tl_kmac_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T82,T125,T126	Yes	T17,T82,T125	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T82,T125	Yes	T17,T82,T125	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T17,T82,T125	Yes	T17,T82,T438	INPUT
tl_kmac_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T76,*T73,*T74	Yes	T76,T73,T74	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T82,*T125,*T126	Yes	T82,T438,T225	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T17,T82,T125	Yes	T17,T82,T125	INPUT
tl_aes_o.d_ready	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T107,T125,T114	Yes	T107,T125,T114	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T107,T125,T114	Yes	T107,T125,T114	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T107,T125,T114	Yes	T107,T125,T114	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T107,T125,T114	Yes	T107,T125,T114	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T107,T125,T114	Yes	T107,T125,T114	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T74,T75,T127	Yes	T74,T75,T127	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T107,T125,T114	Yes	T107,T125,T114	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T107,T125,T114	Yes	T107,T125,T114	INPUT
tl_aes_i.d_error	Yes	Yes	T74,T75,T128	Yes	T74,T75,T127	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T107,T125,T114	Yes	T107,T125,T114	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T107,T125,T114	Yes	T107,T125,T114	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T107,T125,T114	Yes	T107,T125,T114	INPUT
tl_aes_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T74,*T75,*T127	Yes	T73,T74,T75	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T74,T75,T127	Yes	T74,T75,T127	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T107,*T125,*T114	Yes	T107,T125,T114	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T107,T125,T114	Yes	T107,T125,T114	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T76,*T73,*T74	Yes	T76,T73,T74	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T76,*T74,*T75	Yes	T76,T73,T74	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T125,*T122,*T126	Yes	T4,T56,T125	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T76,*T73,*T74	Yes	T76,T73,T74	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T74,T75,T127	Yes	T74,T75,T127	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_error	Yes	Yes	T73,T75,T127	Yes	T73,T75,T127	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T76,*T74,*T75	Yes	T76,T73,T74	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T74,T75,T127	Yes	T74,T75,T127	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T125,*T122,*T126	Yes	T125,T122,T126	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T76,*T73,*T74	Yes	T76,T73,T74	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_sink	Yes	Yes	T74,T75,T127	Yes	T73,T74,T75	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T76,*T74,*T75	Yes	T76,T73,T74	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T74,T75,T127	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T125,*T122,*T126	Yes	T125,T122,T126	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn1_o.d_ready	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T76,*T73,*T74	Yes	T76,T73,T74	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_edn1_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_edn1_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T76,*T74,*T75	Yes	T76,T74,T75	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T125,*T122,*T126	Yes	T125,T122,T126	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T17,T18,T1	Yes	T17,T18,T1	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T17,T18	Yes	T6,T17,T18	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T6,T17,T18	Yes	T6,T17,T18	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T6,T17,T18	Yes	T6,T17,T18	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T6,T17,T18	Yes	T6,T17,T18	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T6,T17,T18	Yes	T6,T17,T18	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T6,T17,T18	Yes	T6,T17,T18	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T73,T127,T128	Yes	T73,T127,T128	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T17,T18,T104	Yes	T17,T18,T104	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T17,T18	Yes	T6,T17,T18	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T6,T17,T129	Yes	T6,T17,T18	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T73,T74,T127	Yes	T73,T74,T127	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T73,T74,T127	Yes	T73,T74,T75	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T6,*T17,*T18	Yes	T6,T17,T18	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T6,T17,T18	Yes	T6,T17,T18	INPUT
tl_otbn_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T68,*T77,*T197	Yes	T68,T77,T197	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_otbn_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_otbn_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T68,*T77,*T197	Yes	T68,T77,T197	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T56	Yes	T4,T5,T56	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T4,T56,T57	Yes	T4,T56,T57	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T56,T57	Yes	T4,T56,T57	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T4,T56,T57	Yes	T4,T56,T57	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T4,T56,T57	Yes	T4,T56,T57	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T4,T56,T57	Yes	T4,T56,T57	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T76,*T73,*T74	Yes	T76,T73,T74	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T4,T56,T57	Yes	T4,T56,T57	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T4,T56,T57	Yes	T4,T56,T57	INPUT
tl_keymgr_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T4,T56,T57	Yes	T4,T56,T57	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T56,T57	Yes	T4,T56,T57	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T4,T56,T57	Yes	T4,T56,T57	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T76,*T73,*T74	Yes	T76,T73,T74	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T4,*T56,*T57	Yes	T4,T56,T57	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T4,T56,T57	Yes	T4,T56,T57	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T6,T45	Yes	T4,T6,T45	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T10,*T73,*T74	Yes	T10,T73,T74	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T10,T73,T74	Yes	T10,T73,T74	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T74,T75,T127	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T10,*T74,*T75	Yes	T10,T73,T74	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T74,T75,T127	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T73,T74,T127	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T178,T182,T183	Yes	T178,T182,T183	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T54,T174	Yes	T4,T5,T56	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T5,T54,T174	Yes	T4,T5,T56	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T74,*T75,*T127	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T127	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T174,*T115,*T178	Yes	T174,T293,T115	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T4,T5,T56	Yes	T4,T5,T56	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T44	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range