Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T176,T177,T300
0	1	Covered	T176,T177,T300
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T177,T300
1	Covered	T176,T177,T300

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T177,T300
1	Covered	T176,T177,T300

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T176,T177,T300
1	1	Covered	T176,T177,T300

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T176,T177,T300
1	0	Covered	T176,T177,T300
1	1	Covered	T176,T177,T300

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T176,T177,T300

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T177,T300
0	Covered	T176,T177,T300

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T177,T300
0	Covered	T176,T177,T300

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	966537506	952274422	0	0
CheckNGreaterZero_A	1988	1988	0	0
GntImpliesReady_A	966537506	8461	0	0
GntImpliesValid_A	966537506	8461	0	0
GrantKnown_A	966537506	952274422	0	0
IdxKnown_A	966537506	952274422	0	0
IndexIsCorrect_A	966537506	8461	0	0
NoReadyValidNoGrant_A	966537506	0	0	0
Priority_A	966537506	8461	0	0
ReadyAndValidImplyGrant_A	966537506	8461	0	0
ReqAndReadyImplyGrant_A	966537506	8461	0	0
ReqImpliesValid_A	966537506	8461	0	0
ValidKnown_A	966537506	952274422	0	0
gen_data_port_assertion.DataFlow_A	966537506	8461	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966537506	952274422	0	0
T4	268448	268436	0	0
T5	1704210	1703976	0	0
T6	254450	254246	0	0
T17	496798	496572	0	0
T18	306880	306756	0	0
T44	479404	479382	0	0
T45	277216	277092	0	0
T56	270810	270798	0	0
T59	77282	77180	0	0
T82	161878	161754	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1988	1988	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T44	2	2	0	0
T45	2	2	0	0
T56	2	2	0	0
T59	2	2	0	0
T82	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966537506	8461	0	0
T51	308514	0	0	0
T83	252982	0	0	0
T176	203458	2820	0	0
T177	0	2821	0	0
T228	797938	0	0	0
T261	196046	0	0	0
T300	0	2820	0	0
T303	733374	0	0	0
T304	426754	0	0	0
T305	687612	0	0	0
T306	293090	0	0	0
T307	130768	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966537506	8461	0	0
T51	308514	0	0	0
T83	252982	0	0	0
T176	203458	2820	0	0
T177	0	2821	0	0
T228	797938	0	0	0
T261	196046	0	0	0
T300	0	2820	0	0
T303	733374	0	0	0
T304	426754	0	0	0
T305	687612	0	0	0
T306	293090	0	0	0
T307	130768	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966537506	952274422	0	0
T4	268448	268436	0	0
T5	1704210	1703976	0	0
T6	254450	254246	0	0
T17	496798	496572	0	0
T18	306880	306756	0	0
T44	479404	479382	0	0
T45	277216	277092	0	0
T56	270810	270798	0	0
T59	77282	77180	0	0
T82	161878	161754	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966537506	952274422	0	0
T4	268448	268436	0	0
T5	1704210	1703976	0	0
T6	254450	254246	0	0
T17	496798	496572	0	0
T18	306880	306756	0	0
T44	479404	479382	0	0
T45	277216	277092	0	0
T56	270810	270798	0	0
T59	77282	77180	0	0
T82	161878	161754	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966537506	8461	0	0
T51	308514	0	0	0
T83	252982	0	0	0
T176	203458	2820	0	0
T177	0	2821	0	0
T228	797938	0	0	0
T261	196046	0	0	0
T300	0	2820	0	0
T303	733374	0	0	0
T304	426754	0	0	0
T305	687612	0	0	0
T306	293090	0	0	0
T307	130768	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966537506	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966537506	8461	0	0
T51	308514	0	0	0
T83	252982	0	0	0
T176	203458	2820	0	0
T177	0	2821	0	0
T228	797938	0	0	0
T261	196046	0	0	0
T300	0	2820	0	0
T303	733374	0	0	0
T304	426754	0	0	0
T305	687612	0	0	0
T306	293090	0	0	0
T307	130768	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966537506	8461	0	0
T51	308514	0	0	0
T83	252982	0	0	0
T176	203458	2820	0	0
T177	0	2821	0	0
T228	797938	0	0	0
T261	196046	0	0	0
T300	0	2820	0	0
T303	733374	0	0	0
T304	426754	0	0	0
T305	687612	0	0	0
T306	293090	0	0	0
T307	130768	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966537506	8461	0	0
T51	308514	0	0	0
T83	252982	0	0	0
T176	203458	2820	0	0
T177	0	2821	0	0
T228	797938	0	0	0
T261	196046	0	0	0
T300	0	2820	0	0
T303	733374	0	0	0
T304	426754	0	0	0
T305	687612	0	0	0
T306	293090	0	0	0
T307	130768	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966537506	8461	0	0
T51	308514	0	0	0
T83	252982	0	0	0
T176	203458	2820	0	0
T177	0	2821	0	0
T228	797938	0	0	0
T261	196046	0	0	0
T300	0	2820	0	0
T303	733374	0	0	0
T304	426754	0	0	0
T305	687612	0	0	0
T306	293090	0	0	0
T307	130768	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966537506	952274422	0	0
T4	268448	268436	0	0
T5	1704210	1703976	0	0
T6	254450	254246	0	0
T17	496798	496572	0	0
T18	306880	306756	0	0
T44	479404	479382	0	0
T45	277216	277092	0	0
T56	270810	270798	0	0
T59	77282	77180	0	0
T82	161878	161754	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966537506	8461	0	0
T51	308514	0	0	0
T83	252982	0	0	0
T176	203458	2820	0	0
T177	0	2821	0	0
T228	797938	0	0	0
T261	196046	0	0	0
T300	0	2820	0	0
T303	733374	0	0	0
T304	426754	0	0	0
T305	687612	0	0	0
T306	293090	0	0	0
T307	130768	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T176,T177,T300
0	1	Covered	T176,T177,T300
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T177,T300
1	Covered	T176,T177,T300

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T177,T300
1	Covered	T176,T177,T300

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T176,T177,T300
1	1	Covered	T176,T177,T300

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T176,T177,T300
1	0	Covered	T176,T177,T300
1	1	Covered	T176,T177,T300

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T176,T177,T300

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T177,T300
0	Covered	T176,T177,T300

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T177,T300
0	Covered	T176,T177,T300

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	483268753	476137211	0	0
CheckNGreaterZero_A	994	994	0	0
GntImpliesReady_A	483268753	5277	0	0
GntImpliesValid_A	483268753	5277	0	0
GrantKnown_A	483268753	476137211	0	0
IdxKnown_A	483268753	476137211	0	0
IndexIsCorrect_A	483268753	5277	0	0
NoReadyValidNoGrant_A	483268753	0	0	0
Priority_A	483268753	5277	0	0
ReadyAndValidImplyGrant_A	483268753	5277	0	0
ReqAndReadyImplyGrant_A	483268753	5277	0	0
ReqImpliesValid_A	483268753	5277	0	0
ValidKnown_A	483268753	476137211	0	0
gen_data_port_assertion.DataFlow_A	483268753	5277	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	476137211	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	994	994	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	5277	0	0
T51	154257	0	0	0
T83	126491	0	0	0
T176	101729	1759	0	0
T177	0	1759	0	0
T228	398969	0	0	0
T261	98023	0	0	0
T300	0	1759	0	0
T303	366687	0	0	0
T304	213377	0	0	0
T305	343806	0	0	0
T306	146545	0	0	0
T307	65384	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	5277	0	0
T51	154257	0	0	0
T83	126491	0	0	0
T176	101729	1759	0	0
T177	0	1759	0	0
T228	398969	0	0	0
T261	98023	0	0	0
T300	0	1759	0	0
T303	366687	0	0	0
T304	213377	0	0	0
T305	343806	0	0	0
T306	146545	0	0	0
T307	65384	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	476137211	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	476137211	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	5277	0	0
T51	154257	0	0	0
T83	126491	0	0	0
T176	101729	1759	0	0
T177	0	1759	0	0
T228	398969	0	0	0
T261	98023	0	0	0
T300	0	1759	0	0
T303	366687	0	0	0
T304	213377	0	0	0
T305	343806	0	0	0
T306	146545	0	0	0
T307	65384	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	5277	0	0
T51	154257	0	0	0
T83	126491	0	0	0
T176	101729	1759	0	0
T177	0	1759	0	0
T228	398969	0	0	0
T261	98023	0	0	0
T300	0	1759	0	0
T303	366687	0	0	0
T304	213377	0	0	0
T305	343806	0	0	0
T306	146545	0	0	0
T307	65384	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	5277	0	0
T51	154257	0	0	0
T83	126491	0	0	0
T176	101729	1759	0	0
T177	0	1759	0	0
T228	398969	0	0	0
T261	98023	0	0	0
T300	0	1759	0	0
T303	366687	0	0	0
T304	213377	0	0	0
T305	343806	0	0	0
T306	146545	0	0	0
T307	65384	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	5277	0	0
T51	154257	0	0	0
T83	126491	0	0	0
T176	101729	1759	0	0
T177	0	1759	0	0
T228	398969	0	0	0
T261	98023	0	0	0
T300	0	1759	0	0
T303	366687	0	0	0
T304	213377	0	0	0
T305	343806	0	0	0
T306	146545	0	0	0
T307	65384	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	5277	0	0
T51	154257	0	0	0
T83	126491	0	0	0
T176	101729	1759	0	0
T177	0	1759	0	0
T228	398969	0	0	0
T261	98023	0	0	0
T300	0	1759	0	0
T303	366687	0	0	0
T304	213377	0	0	0
T305	343806	0	0	0
T306	146545	0	0	0
T307	65384	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	476137211	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	5277	0	0
T51	154257	0	0	0
T83	126491	0	0	0
T176	101729	1759	0	0
T177	0	1759	0	0
T228	398969	0	0	0
T261	98023	0	0	0
T300	0	1759	0	0
T303	366687	0	0	0
T304	213377	0	0	0
T305	343806	0	0	0
T306	146545	0	0	0
T307	65384	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T176,T177,T300
0	1	Covered	T176,T177,T300
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T177,T300
1	Covered	T176,T177,T300

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T177,T300
1	Covered	T176,T177,T300

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T176,T177,T300
1	1	Covered	T176,T177,T300

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T176,T177,T300
1	0	Covered	T176,T177,T300
1	1	Covered	T176,T177,T300

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T176,T177,T300

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T177,T300
0	Covered	T176,T177,T300

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T177,T300
0	Covered	T176,T177,T300

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	483268753	476137211	0	0
CheckNGreaterZero_A	994	994	0	0
GntImpliesReady_A	483268753	3184	0	0
GntImpliesValid_A	483268753	3184	0	0
GrantKnown_A	483268753	476137211	0	0
IdxKnown_A	483268753	476137211	0	0
IndexIsCorrect_A	483268753	3184	0	0
NoReadyValidNoGrant_A	483268753	0	0	0
Priority_A	483268753	3184	0	0
ReadyAndValidImplyGrant_A	483268753	3184	0	0
ReqAndReadyImplyGrant_A	483268753	3184	0	0
ReqImpliesValid_A	483268753	3184	0	0
ValidKnown_A	483268753	476137211	0	0
gen_data_port_assertion.DataFlow_A	483268753	3184	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	476137211	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	994	994	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	3184	0	0
T51	154257	0	0	0
T83	126491	0	0	0
T176	101729	1061	0	0
T177	0	1062	0	0
T228	398969	0	0	0
T261	98023	0	0	0
T300	0	1061	0	0
T303	366687	0	0	0
T304	213377	0	0	0
T305	343806	0	0	0
T306	146545	0	0	0
T307	65384	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	3184	0	0
T51	154257	0	0	0
T83	126491	0	0	0
T176	101729	1061	0	0
T177	0	1062	0	0
T228	398969	0	0	0
T261	98023	0	0	0
T300	0	1061	0	0
T303	366687	0	0	0
T304	213377	0	0	0
T305	343806	0	0	0
T306	146545	0	0	0
T307	65384	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	476137211	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	476137211	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	3184	0	0
T51	154257	0	0	0
T83	126491	0	0	0
T176	101729	1061	0	0
T177	0	1062	0	0
T228	398969	0	0	0
T261	98023	0	0	0
T300	0	1061	0	0
T303	366687	0	0	0
T304	213377	0	0	0
T305	343806	0	0	0
T306	146545	0	0	0
T307	65384	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	3184	0	0
T51	154257	0	0	0
T83	126491	0	0	0
T176	101729	1061	0	0
T177	0	1062	0	0
T228	398969	0	0	0
T261	98023	0	0	0
T300	0	1061	0	0
T303	366687	0	0	0
T304	213377	0	0	0
T305	343806	0	0	0
T306	146545	0	0	0
T307	65384	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	3184	0	0
T51	154257	0	0	0
T83	126491	0	0	0
T176	101729	1061	0	0
T177	0	1062	0	0
T228	398969	0	0	0
T261	98023	0	0	0
T300	0	1061	0	0
T303	366687	0	0	0
T304	213377	0	0	0
T305	343806	0	0	0
T306	146545	0	0	0
T307	65384	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	3184	0	0
T51	154257	0	0	0
T83	126491	0	0	0
T176	101729	1061	0	0
T177	0	1062	0	0
T228	398969	0	0	0
T261	98023	0	0	0
T300	0	1061	0	0
T303	366687	0	0	0
T304	213377	0	0	0
T305	343806	0	0	0
T306	146545	0	0	0
T307	65384	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	3184	0	0
T51	154257	0	0	0
T83	126491	0	0	0
T176	101729	1061	0	0
T177	0	1062	0	0
T228	398969	0	0	0
T261	98023	0	0	0
T300	0	1061	0	0
T303	366687	0	0	0
T304	213377	0	0	0
T305	343806	0	0	0
T306	146545	0	0	0
T307	65384	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	476137211	0	0
T4	134224	134218	0	0
T5	852105	851988	0	0
T6	127225	127123	0	0
T17	248399	248286	0	0
T18	153440	153378	0	0
T44	239702	239691	0	0
T45	138608	138546	0	0
T56	135405	135399	0	0
T59	38641	38590	0	0
T82	80939	80877	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483268753	3184	0	0
T51	154257	0	0	0
T83	126491	0	0	0
T176	101729	1061	0	0
T177	0	1062	0	0
T228	398969	0	0	0
T261	98023	0	0	0
T300	0	1061	0	0
T303	366687	0	0	0
T304	213377	0	0	0
T305	343806	0	0	0
T306	146545	0	0	0
T307	65384	0	0	0