Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	994	994	0	0
OutputsKnown_A	120436809	119751625	0	0
gen_no_flops.OutputDelay_A	120436809	119751625	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	994	994	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120436809	119751625	0	0
T4	322811	322529	0	0
T5	205480	204875	0	0
T6	33196	32522	0	0
T17	60780	60356	0	0
T18	37762	37206	0	0
T44	576827	576069	0	0
T45	34677	33634	0	0
T56	326177	325362	0	0
T59	10175	9648	0	0
T82	26512	26028	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120436809	119751625	0	0
T4	322811	322529	0	0
T5	205480	204875	0	0
T6	33196	32522	0	0
T17	60780	60356	0	0
T18	37762	37206	0	0
T44	576827	576069	0	0
T45	34677	33634	0	0
T56	326177	325362	0	0
T59	10175	9648	0	0
T82	26512	26028	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	994	994	0	0
OutputsKnown_A	120436809	119751625	0	0
gen_no_flops.OutputDelay_A	120436809	119751625	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	994	994	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T56	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120436809	119751625	0	0
T4	322811	322529	0	0
T5	205480	204875	0	0
T6	33196	32522	0	0
T17	60780	60356	0	0
T18	37762	37206	0	0
T44	576827	576069	0	0
T45	34677	33634	0	0
T56	326177	325362	0	0
T59	10175	9648	0	0
T82	26512	26028	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120436809	119751625	0	0
T4	322811	322529	0	0
T5	205480	204875	0	0
T6	33196	32522	0	0
T17	60780	60356	0	0
T18	37762	37206	0	0
T44	576827	576069	0	0
T45	34677	33634	0	0
T56	326177	325362	0	0
T59	10175	9648	0	0
T82	26512	26028	0	0