Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.34			99.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_edn1	99.02			99.02
tb.dut.top_earlgrey.u_edn0	99.25			99.25

---

Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.02			99.02

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.02			99.02

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.25			99.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.25			99.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	78	75	96.15
Total Bits	1210	1202	99.34
Total Bits 0->1	605	602	99.50
Total Bits 1->0	605	600	99.17

Ports	78	75	96.15
Port Bits	1210	1202	99.34
Port Bits 0->1	605	602	99.50
Port Bits 1->0	605	600	99.17

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20:16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T76,*T73,*T74	Yes	T76,T73,T74	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T74,*T75	Yes	T76,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T125,*T122,*T126	Yes	T125,T122,T126	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i[0].edn_req	Yes	Yes	T57,T125,T122	Yes	T57,T125,T122	INPUT
edn_i[1].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[2].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[3].edn_req	Yes	Yes	T438,T116,T303	Yes	T438,T116,T303	INPUT
edn_i[4].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[5].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[6].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[7].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T57,T122,T126	Yes	T57,T125,T122	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T265,T266,T267	Yes	T125,T122,T126	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T57,T125,T122	Yes	T57,T125,T122	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[1].edn_fips	No	No		Yes	T111,T112,T152	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T5,T6,T44	Yes	T5,T6,T45	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T109,T110	Yes	T111,T112,T113	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T438,T116,T303	Yes	T438,T116,T303	OUTPUT
edn_o[3].edn_fips	No	No		Yes	T116,T303,T117	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T438,T116,T303	Yes	T438,T116,T303	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T6,T44,T17	Yes	T4,T6,T45	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T701	Yes	T111,T702,T703	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T265,T266,T267	Yes	T125,T295,T265	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T265,T266,T267	Yes	T122,T111,T336	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[7].edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[7].edn_fips	Yes	Yes	T265,T266,T267	Yes	T265,T266,T267	OUTPUT
edn_o[7].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T376,T110,T699	Yes	T125,T122,T126	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T123,T265,T266	Yes	T123,T265,T266	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T123,T78,T80	Yes	T123,T78,T80	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T80,T249	Yes	T78,T80,T249	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T80,T249	Yes	T78,T80,T249	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T78,T80,T704	Yes	T78,T80,T704	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T78,T80,T249	Yes	T78,T80,T249	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T78,T80,T249	Yes	T78,T80,T249	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T123,T78,T80	Yes	T123,T78,T80	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T78,T80,T704	Yes	T78,T80,T704	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T122,T294,T321	Yes	T122,T294,T321	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T294,T321,T322	Yes	T294,T321,T322	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1

	Total	Covered	Percent
Totals	50	48	96.00
Total Bits	714	707	99.02
Total Bits 0->1	357	354	99.16
Total Bits 1->0	357	353	98.88

Ports	50	48	96.00
Port Bits	714	707	99.02
Port Bits 0->1	357	354	99.16
Port Bits 1->0	357	353	98.88

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20:19]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T125,*T122,*T126	Yes	T125,T122,T126	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T125,*T122,*T126	Yes	T125,T122,T126	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T76,*T73,*T74	Yes	T76,T73,T74	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_valid	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_o.a_ready	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
tl_o.d_sink	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T74,*T75	Yes	T76,T74,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T125,*T122,*T126	Yes	T125,T122,T126	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
edn_i[0].edn_req	Yes	Yes	T122,T111,T336	Yes	T122,T111,T336	INPUT
edn_i[1].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[2].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[3].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[4].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[5].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[6].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[7].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_o[0].edn_bus[31:0]	Yes	Yes	T122,T111,T336	Yes	T122,T111,T336	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T265,T266,T267	Yes	T122,T111,T336	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T122,T111,T336	Yes	T122,T111,T336	OUTPUT
edn_o[1].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[1].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[1].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
csrng_cmd_o.genbits_ready	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T122,T123,T111	Yes	T125,T122,T126	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T125,T122,T126	Yes	T122,T111,T336	INPUT
csrng_cmd_i.genbits_fips	No	No		Yes	T376,T699,T700	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T265,T266,T267	Yes	T265,T266,T267	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T80,T60	Yes	T78,T80,T60	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T80,T249	Yes	T78,T80,T249	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T80,T249	Yes	T78,T80,T249	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T78,T80,T704	Yes	T78,T80,T704	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T78,T80,T249	Yes	T78,T80,T249	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T78,T80,T249	Yes	T78,T80,T249	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T80,T60	Yes	T78,T80,T60	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T78,T80,T704	Yes	T78,T80,T704	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T122,T294,T321	Yes	T122,T294,T321	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T294,T321,T322	Yes	T294,T321,T322	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0

	Total	Covered	Percent
Totals	78	74	94.87
Total Bits	1208	1199	99.25
Total Bits 0->1	604	601	99.50
Total Bits 1->0	604	598	99.01

Ports	78	74	94.87
Port Bits	1208	1199	99.25
Port Bits 0->1	604	601	99.50
Port Bits 1->0	604	598	99.01

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T76,*T73,*T74	Yes	T76,T73,T74	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T125,T122,T126	Yes	T125,T122,T126	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T74,T75,T127	Yes	T73,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T74,*T75	Yes	T76,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T74,T75,T127	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T125,*T122,*T126	Yes	T125,T122,T126	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i[0].edn_req	Yes	Yes	T57,T125,T126	Yes	T57,T125,T126	INPUT
edn_i[1].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[2].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[3].edn_req	Yes	Yes	T438,T116,T303	Yes	T438,T116,T303	INPUT
edn_i[4].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[5].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[6].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[7].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T57,T126,T225	Yes	T57,T125,T126	OUTPUT
edn_o[0].edn_fips	No	No		Yes	T125,T126,T225	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T57,T125,T126	Yes	T57,T125,T126	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[1].edn_fips	No	No		Yes	T111,T112,T152	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T5,T6,T44	Yes	T5,T6,T45	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T109,T110	Yes	T111,T112,T113	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T438,T116,T303	Yes	T438,T116,T303	OUTPUT
edn_o[3].edn_fips	No	No		Yes	T116,T303,T117	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T438,T116,T303	Yes	T438,T116,T303	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T6,T44,T17	Yes	T4,T6,T45	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T701	Yes	T111,T702,T703	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T265,T266,T267	Yes	T125,T295,T265	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T265,T266,T267	Yes	T122,T111,T336	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[7].edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[7].edn_fips	Yes	Yes	T265,T266,T267	Yes	T265,T266,T267	OUTPUT
edn_o[7].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T5,T6,T44	Yes	T4,T5,T6	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T376,T110,T699	Yes	T125,T122,T126	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T123,T265,T266	Yes	T123,T265,T266	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T123,T78,T80	Yes	T123,T78,T80	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T80,T81	Yes	T78,T80,T81	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T78,T80,T60	Yes	T78,T80,T60	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T78,T80,T81	Yes	T80,T81,T268	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T80,T81,T268	Yes	T78,T80,T81	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T123,T78,T80	Yes	T123,T78,T80	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T78,T80,T60	Yes	T78,T80,T60	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T122,T294,T321	Yes	T122,T294,T321	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T294,T321,T322	Yes	T294,T321,T322	OUTPUT

*Tests covering at least one bit in the range